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2022-04-25clk: meson: add minimal driver for axg-ao clocksVyacheslav Bocharov
Add minimal driver AO clocks on meson AXG family. Only ADC related clocks are supported. Signed-off-by: Vyacheslav Bocharov <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-04-18rockchip: rk3066: add clock driver for rk3066 socPaweł Jarosz
Add the clock driver for the rk3066 platform. Derived from the rk3288 and rk3188 driver it supports only a bare minimum to bring up the system to reduce the TPL size for: SDRAM clock configuration. The boot devices NAND, EMMC, SDMMC, SPI. A UART for the debug messages (fixed) at 115200n8. A SARADC for the recovery button. A TIMER for the delays (fixed). There's support for two possible frequencies, the safe 600MHz which will work with default pmic settings and will be set to get away from the 24MHz default and the maximum of 1.416Ghz, which boards can set if they were able to get pmic support for it. After the clock tree is set during the TPL probe there's no parent update support. In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c obtain the (fixed) clk_get_rate from the clock driver instead of platdata. The rk3066 cru node has a number of assigned-clocks properties that call the .set_rate() function. Add them to the list so that they return a 0 instead of -ENOENT. Signed-off-by: Paweł Jarosz <[email protected]> Signed-off-by: Johan Jonker <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-04-18rockchip: clk: add clocks to px30_clk_enableChris Morgan
Add the HCLK_OTG, HCLK_SFC, and SCLK_SFC clocks to px30_clk_enable. Without this change U-Boot reports an error of "Enable clock-controller@ff2b0000 failed" on boot when using the SFC or USB in U-Boot. Signed-off-by: Chris Morgan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-04-13clk: imx8mp: Fix 24M and 32k clockMarek Vasut
Fix registration of 24M and 32k clock, those got applied or rebased incorrectly, so fill in the correct code. Fixes: 7a2c3be95a5 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Marek Vasut <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Peng Fan <[email protected]> Cc: Stefano Babic <[email protected]> Cc: Ye Li <[email protected]>
2022-04-12clk: imx8mp: Add ECSPI clocksElmar Albert
Add clock tables required for bing up ECSPI interfaces Signed-off-by: Elmar Albert <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Peng Fan <[email protected]> Cc: Stefano Babic <[email protected]> Cc: uboot-imx <[email protected]> Signed-off-by: Elmar Albert <[email protected]> Reviewed-by: Fabio Estevam <[email protected]>
2022-04-12clk: imxrt: Use dts for anatop base addressJesse Taube
In Linux IMX and IMXRT use the device tree to hold the anatop address. The anatop is used in clock drivers as it controls the internal PLLs This will move the macro from asm/arch-imxrt to the device tree. This presumably should also be done with the other IMX boards as well. Signed-off-by: Jesse Taube <[email protected]>
2022-04-12clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clockMarek Vasut
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain. Signed-off-by: Marek Vasut <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Peng Fan <[email protected]> Cc: Stefano Babic <[email protected]>
2022-04-12clk: imx8m: reduce rate table duplicationAngus Ainslie
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock driver. 43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common place") Signed-off-by: Angus Ainslie <[email protected]> Tested-by: Adam Ford <[email protected]> #imx8mm-beacon
2022-04-12clk: imx8mq: Add a clock driver for the imx8mqAngus Ainslie
This is a DM clock driver based off the imx8mm u-boot driver and the linux kernel driver. All of the PLLs and clocks are initialized so the subsystems below are functional and tested. 1) USB host and peripheral 2) ECSPI 3) UART 4) I2C all busses 5) USDHC for eMMC support 6) USB storage 7) GPIO 8) DRAM Signed-off-by: Angus Ainslie <[email protected]> Acked-by: Sean Anderson <[email protected]>
2022-04-12clk: imx8mm: add pwm clocks supportTommaso Merciai
Add clocks support for the PWM controllers. This is ported from Linux v5.17-rc8. Signed-off-by: Tommaso Merciai <[email protected]>
2022-04-05Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
2022-04-05clk: zynqmp: Add support for for DP audio/video clocksMichal Simek
Add support for getting rate for DP audio and video clocks. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/8792efe1fd9715f7c8a2e1e24f0454fb5b25d833.1648552434.git.michal.simek@xilinx.com
2022-03-30clk: Use generic CCF ops where possibleSean Anderson
This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Claudiu Beznea <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <[email protected]>
2022-03-30clk: ccf: Add some helper functions for clock opsSean Anderson
Most CCF drivers follow a common pattern where their clock ops defer the actual operation to the backing CCF clock. Add some generic implementations of these functions to reduce duplication of code. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-03-30clk: Consolidate some clock functionsSean Anderson
These functions are exactly the same as their "nodev" varients, except they accept a device and not an ofnode. Rewrite them to just call the other function. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-03-30clk: Make clk_free return voidSean Anderson
Most callers of this function do not check the return value, and it is unclear what action they should take if it fails. If a function is freeing multiple clocks, it should not stop just because the first one failed. Since the callbacks can no longer fail, just convert the return type to void. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-03-30clk: Make rfree return voidSean Anderson
When freeing a clock there is not much we can do if there is an error, and most callers do not actually check the return value. Even e.g. checking to make sure that clk->id is valid should have been done in request() in the first place (unless someone is messing with the driver behind our back). Just return void and don't bother returning an error. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-03-28Merge tag 'v2022.04-rc5' into nextTom Rini
Prepare v2022.04-rc5
2022-03-15k210: use the board vendor name rather than the marketing nameDamien Le Moal
"kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal <[email protected]> Signed-off-by: Niklas Cassel <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2022-03-02clk: scmi: register scmi clocks with CCFEtienne Carriere
Implements SCMI APIs to retrieve the number exposed SCMI clocks using SCMI_PROTOCOL_ATTRIBUTES messages and the names of the clocks using SCMI_CLOCK_ATTRIBUTES messages. This change updates sandbox SCMI clock test driver to manage these 2 new message IDs. Cc: Lukasz Majewski <[email protected]> Cc: Sean Anderson <[email protected]> Cc: Clement Leger <[email protected]> Cc: Patrick Delaunay <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]> Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Etienne Carriere <[email protected]>
2022-03-02scmi: change parameter dev in devm_scmi_process_msgEtienne Carriere
Changes devm_scmi_process_msg() first argument from target parent device to current SCMI device and lookup the SCMI agent device among SCMI device parents for find the SCMI agent operator needed for communication with the firmware. This change is needed in order to support CCF in clk_scmi driver unless what CCF will fail to find the right udevice related to exposed SCMI clocks. This patch allows to simplify the caller sequence, using SCMI device reference as parameter instead of knowing SCMI uclass topology. This change also adds some protection in case devm_scmi_process_msg() API function is called for an invalid device type. Cc: Lukasz Majewski <[email protected]> Cc: Sean Anderson <[email protected]> Cc: Jaehoon Chung <[email protected]> Cc: Patrick Delaunay <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]> Signed-off-by: Etienne Carriere <[email protected]>
2022-02-25clk: ccf: correct the test on the parent uclass in clk_enable/clk_disablePatrick Delaunay
It is safe to check if the uclass id on the device is UCLASS_CLK before to call the clk_ functions, but today this comparison is not done on the device used in API: clkp->dev->parent but on the device himself: clkp->dev. This patch corrects this behavior and tests if the parent device is a clock device before to call the clock API, clk_enable or clk_disable, on this device. Fixes: 0520be0f67e3 ("clk: prograte clk enable/disable to parent") Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Sean Anderson <[email protected]>
2022-02-25clk: Add clk_get_by_name_optionalSean Anderson
This adds a helper function for clk_get_by_name in cases where the clock is optional. Hopefully this helps point driver writers in the right direction. Also convert some existing users. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: Inline clk_get_*_optionalSean Anderson
The optional varients of clk_get_* functions are just simple wrappers. Reduce code size a bit by inlining them. On platforms where it is not used (most of them), it will not be compiled in any more. On platforms where they are used, the inlined branch should not cause any significant growth. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: Rename clk_get_optional_nodevSean Anderson
This normalizes the name of this accessor function to put "_optional" last. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: cdce9xx: Convert .of_xlate to .requestSean Anderson
This xlate function just performs some checking. We can do this in request() instead and use the default xlate. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Tero Kristo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: versaclock: Remove xlate functionSean Anderson
This function is the same as the default xlate. Remove it. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Adam Ford <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: Remove no-op request and rfree callbacksSean Anderson
These callbacks are optional. Remove ones which do nothing. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: Rename ICS8N3QV01 to CLK_ICS8N3QV01Sean Anderson
This driver was missing a clock prefix. Add one. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: Alphabetize KconfigSean Anderson
This alphabetizes the Kconfig for the clock subsystem. This will help people find their clocks, and help prevent merge conflicts. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-24clk: Alphabetize MakefileSean Anderson
This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-19clk: imx: select [SPL_]CLK_COMPOSITE_CCF for imx8mnHeiko Thiery
The clock composite is required when using the clock framework. So select it automatically. Signed-off-by: Heiko Thiery <[email protected]>
2022-02-08clk: clk-k3: Add support for J721S2 SoCDavid Huang
Add support for J721S2 SoC. Signed-off-by: David Huang <[email protected]> Signed-off-by: Aswath Govindraju <[email protected]>
2022-02-05clk: imx: select [SPL_]CLK_COMPOSITE_CCF for imxrt10{20|50}Heiko Thiery
The clock composite is required when using the clock framework. So select it automatically. Signed-off-by: Heiko Thiery <[email protected]> Reviewed-by: Giulio Benetti <[email protected]>
2022-01-20Merge tag 'doc-2022-04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request doc-2022-04-rc1 Replace @return by Return: in code comments.
2022-01-19doc: replace @return by Return:Heinrich Schuchardt
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <[email protected]>
2022-01-19Merge tag 'xilinx-for-v2022.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc1 gpio: - Add modepin driver net: - Save random mac addresses to eth variable zynqmp gem: - Add support for mdio bus DT description - Add support for reset and SGMII phy configuration - Reduce timeout for MDIO accesses zynqmp clk: - Fix clock handling for gem and usb phy: - Add zynqmp phy/serdes driver serial: - Add one missing compatible string microblaze: - Symbol alignement - SPL fixups - Code cleanups zynqmp: - Various dt changes, DP pre-reloc, gem resets, gem clocks - Switch SOM to shared psu configuration - Move dcache handling to firmware driver - Workaround gmii2rgmii DT description issue - Enable broadcasts again - Change firmware enablement logic - Small adjustement in firmware driver versal: - Support new mmc@ DT nodes - Fix run time variable handling - Add missing I2C_PMC ID for power domain
2022-01-18clk: ast2600: Revise MII interface delayDylan Hung
The clock delay of the RMII/RGMII interface is controlled by SCU340~35C. These values are obtained by measurement and experiments so we simply use macro to define them. Signed-off-by: Dylan Hung <[email protected]> Reviewed-by: Ramon Fried <[email protected]>
2022-01-18clk: actions: Add SD/MMC clocksAmit Singh Tomar
This commit adds SD/MMC clocks, and provides .set/get_rate callbacks for SD/MMC device present on Actions OWL S700 SoCs. Signed-off-by: Amit Singh Tomar <[email protected]>
2022-01-18clk: actions: Introduce dummy get/set_rate callbacksAmit Singh Tomar
This commit introduces get/set_rate callbacks, these are dummy at the moment, and can be used to get/set clock for various devices based on the clk id. Signed-off-by: Amit Singh Tomar <[email protected]> Reviewed-by: Sean Anderson <[email protected]>
2022-01-13treewide: invaild -> invalidSean Anderson
Somewhere along the way, someone misspelt "invalid" and it got copied everywhere. Fix it. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Alexander Dahl <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-01-10Merge branch 'next'Tom Rini
Signed-off-by: Tom Rini <[email protected]>
2022-01-07Revert "clk: Detect failure to set defaults"Marek Vasut
This reverts commit 92f1e9a4b31c0bf0f4f61ab823a6a88657323646. The aforementioned patch causes massive breakage on all platforms which have 'assigned-clock' DT property in their DT which references any clock that are not supported by the platform clock driver. That can easily happen either in SPL, or because the clock driver is reduced. Currently it seems all iMX8M are affected and fail to boot altogether. Signed-off-by: Marek Vasut <[email protected]> Cc: Peng Fan <[email protected]> Cc: Simon Glass <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-01-05clk: zynqmp: Fix gem tx/rx/ref clock handlingMichal Simek
gemX_ref clock IDs starts at number 104. Till now it was at gemX_tx location which wasn't correct. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/d073e159b6316707306092a62bccb876cd89a602.1635506016.git.michal.simek@xilinx.com
2022-01-05clk: zynqmp: Add support for setting up clock for USBMichal Simek
USB range is not enabled but for setting up frequency it is needed. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c55c423f48ca8f953a2dfbdcb25068278d8e5ad6.1635506016.git.michal.simek@xilinx.com
2021-12-27Finish conversion of CONFIG_SYS_CLK_FREQ to KconfigTom Rini
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <[email protected]>
2021-12-20Merge tag 'v2022.01-rc4' into nextTom Rini
Prepare v2022.01-rc4
2021-12-15clk: define LOG_CATEGORY for generic and ccf clocksPatrick Delaunay
Define LOG_CATEGORY to allow filtering with log command for generic clock and CCF clocks. This patch also change existing printf, debug and pr_ macro to log_ or dev_ macro. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Sean Anderson <[email protected]>
2021-12-15clk: cosmetic: reorder include filesPatrick Delaunay
Reorder include files in the U-Boot expected order: the common.h header should always be first, followed by other headers in order, then headers with directories, then local files. It is a preliminary step for next patch. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Sean Anderson <[email protected]>
2021-11-23clk: scmi: define LOG_CATEGORYPatrick Delaunay
Define LOG_CATEGORY to allow filtering with log command. Signed-off-by: Patrick Delaunay <[email protected]> Acked-by: Etienne Carriere <[email protected]>