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Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have multiple licenses (in
these cases, dual license) declared in the SPDX-License-Identifier tag.
In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A
or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B"
as per the Linux Kernel style document. Note that parenthesis are
allowed so when they were used before we continue to use them.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <[email protected]>
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We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <[email protected]>
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CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the
driver doesn't have to play any ifdef game.
Also, we can mark zynq_nand_init() as static and get rid
of the mach-specific nand.h header.
This is really a revert of:
"mtd: zynq: nand: Move board_nand_init() function to board.c"
(sha1: 310995d9f91ae56082b49be06fe8c3d01424f8f6)
Signed-off-by: Ezequiel Garcia <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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This driver is currently broken, refusing to initialize properly.
The reason is that get_nand_dev_by_index() was being called before
nand_register(), thus returning a pointer into uninitialized memory.
In other words, the struct mtd_info used by the driver is total junk.
Fix it by getting the correct struct mtd_info, via nand_to_mtd()
on the driver's struct nand_chip.
Tested on a custom board, where the CPU is halted without this patch.
Signed-off-by: Ezequiel Garcia <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add entry for Spansion s25fl208k part.
Signed-off-by: Sean Nyekjaer <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Make the cfi_flash driver compatible with a live device tree.
Signed-off-by: Mario Six <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Add driver for the RPC block in Hyperflash mode. This driver allows
access to a CFI Hyperflash attached to the RPC block and does not
support RPC in SPI mode.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.
Signed-off-by: Vipul Kumar <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.
It would have been better to convert this defconfig entry to Kconfig for
all supported machines/architectures but it has been abandoned due to a
fairly high amount of errors reported by the moveconfig.py tool. This is
due to defines quite often being multiplications of values/other defines
not correctly handled.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND support.
For now, the only board using it is the CHIP pro.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.
Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.
There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.
The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Executing a command is matter of always doing the following sequence:
* Waiting for the FIFO to be empty so we can fill it with the new
command.
* Clearing the status register.
* Writing the command in the FIFO.
* Waiting for the command to finish.
Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.
Add this sanity check before starting any new command.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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The pattern of polling on a status register until a bit is set or a
timeout occurs is repeated multiple times in the driver. Mutualize the
code by introducing the nand_wait_int() helper that does wait for the
bit to flip or returns an error in case of timeout.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Change NFC_SEND_ADR to NFC_SEND_ADDR.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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In the nand_read_buffer() step, the seed is calculated by doing a modulo
by conf->nseeds which is always zero when not using the randomizer (most
of SLC NANDs).
This situation turns out to lead to a run time freeze with certain
toolchains.
Derive this seed only when the randomizer is enabled (and conf->nseeds
logically not zero), exactly like what has been done before with an
identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo
by zero error").
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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When the requested ECC strength does not exactly match the strengths
supported by the ECC engine, the driver is selecting the closest
strength meeting the 'selected_strength > requested_strength'
constraint. Fix the fact that, in this particular case, ecc->strength
value was not updated to match the 'selected_strength'.
For instance, one can encounter this issue when no ECC requirement is
filled in the device tree while the NAND chip minimum requirement is not
a strength/step_size combo natively supported by the ECC engine.
Suggested-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Signed-off-by: Petr Vorel <[email protected]>
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NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.
Signed-off-by: Vipul Kumar <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Make sure the user is notified instead of silently returning an error.
Signed-off-by: Liam Beguin <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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ppc4xx support was removed some time ago. Lets remove the now unused
NAND driver and all its references for this platform as well.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>
Cc: Scott Wood <[email protected]>
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For STM32F4 and F7 SoCx family, a specific stm32.h file exists.
Some common defines are duplicated or even unused in each of
these stm32.h.
Factorize all common definition in arch/arm/include/asm/stm32f.h and keep
specific definitions in each arch/arm/include/asm/arch-stm32fx/stm32.h.
Signed-off-by: Patrice Chotard <[email protected]>
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This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.
And also renamed the file according to kconfig which resembles
proper name.
Signed-off-by: Jagan Teki <[email protected]>
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Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Reported-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Masahiro Yamada <[email protected]>
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Add entry for ISSI IS25LP256 part.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jagan Teki <[email protected]>
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Fixes a bug found on thuban boards, which were for 2 years in
a long-term test with varying temperatures. They showed
problems in u-boot when attaching the ubi partition:
U-Boot# run flash_self_test
Booting from nand
set A...
UBI: attaching mtd1 to ubi0
UBI: scanning is finished
data abort
pc : [<87f97c3c>] lr : [<87f97c28>]
reloc pc : [<8012cc3c>] lr : [<8012cc28>]
sp : 85f686e8 ip : 00000020 fp : 000001f7
r10: 8605ce40 r9 : 85f68ef8 r8 : 0001f000
r7 : 00000001 r6 : 00000006 r5 : 0001f000 r4 : 85f6ecc0
r3 : 00000000 r2 : 44e35000 r1 : 87fcbcd4 r0 : 87fc755b
Flags: nZCv IRQs off FIQs on Mode SVC_32
Resetting CPU ...
Reason is, that accidentially the U-Boot implementation
from __schedule_ubi_work() did not check the flag
ubi->thread_enabled and started with wearleveling work,
but ubi did not have setup all structures at this point
and crashes.
Solve this problem by splitting work scheduling and processing.
Signed-off-by: Richard Weinberger <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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This converts the following to Kconfig:
CONFIG_APBH_DMA
CONFIG_APBH_DMA_BURST
CONFIG_APBH_DMA_BURST8
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Stefan Agner <[email protected]>
[trini: Add in MMC as well]
Signed-off-by: Tom Rini <[email protected]>
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This converts CONFIG_NAND_MXS to Kconfig.
Signed-off-by: Stefan Agner <[email protected]>
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On detach UBI attempts to update fastmap after closing user interfaces
but at this point UBI volumes have already been free()'ed and fastmap
can no longer access these data structures.
Signed-off-by: Martin Townsend <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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Xilinx changes for v2018.03
- Several Kconfig fixes (also moving configs to defconfigs)
- Some DTS updates
- ZynqMP psu rework based on Zynq concept
- Add low level initialization for zc770 and zcu102
- Add support for Zynq zc770 x16 nand configuration
- Add mini nand/emmc ZynqMP targets
- Some arasan nand changes
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The Arasan NFC driver requires the self-init mode,
so it should select it.
Instead of having the config header define the macro,
it's cleaner to select the option at the Kconfig level.
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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This patch corrects the ecc address calculation before updating
to ecc register. The ecc address has to be calculated based on
page, oob and ecc sizes of the device.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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This patch adds support for ondie ecc. As of now
this adds support for micron parts which supports
ondie ecc.
Didn't found any better way to detect ondie ecc
support by a device except sorting out with
manufacture and device id's.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Move common part of ecc structure initialization to
arasan_nand_init() routine.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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The variable cfi_flash_num_flash_banks is defined iff
CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, but it is used
unconditionally in the function cfi_flash_init_dm. This leads to a
undefined variable compile error when CONFIG_SYS_MAX_FLASH_BANKS_DETECT
is not defined, but DM is enabled.
Fix this by always defining the cfi_flash_num_flash_banks variable.
Signed-off-by: Mario Six <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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