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This patch adds support for the ISSI IS25WP02GG QSPI NOR flash device.
Tested on the Versal VMK180
board in dual-parallel QSPI configuration.
Signed-off-by: jeffrey yu <[email protected]>
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This part is an FRAM, but can be used through the spi-nor generic code.
Signed-off-by: [email protected]
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Peng Fan (OSS) <[email protected]> says:
This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR
instances.
Many files declare DECLARE_GLOBAL_DATA_PTR and include
asm/global_data.h even though gd is never used. In these cases,
asm/global_data.h is effectively treated as a proxy header, which is
not a good practice.
Following the Include What You Use principle, files should include
only the headers they actually depend on, rather than relying on
global_data.h indirectly. This approach is also adopted in Linux kernel
[1].
The first few patches are prepartion to avoid building break after
remove the including of global_data.h.
A script is for filtering the files:
list=`find . -name "*.[ch]"`
for source in ${list}
do
result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}`
if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then
echo "Found in ${source}"
result=`sed -n '/\<gd\>/p' ${source}`
result2=`sed -n '/\<gd_/p' ${source}`
result3=`sed -n '/\<gd->/p' ${source}`
if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then
echo "Cleanup ${source}"
sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source}
sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source}
sed -i '/global_data.h/d' ${source}
git add ${source}
fi
fi
done
[1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf
CI: https://github.com/u-boot/u-boot/pull/865
Link: https://lore.kernel.org/r/[email protected]
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Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.
Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.
Reviewed-by: Patrice Chotard <[email protected]> #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal <[email protected]> #TI boards
Acked-by: Yao Zi <[email protected]> #TH1520
Signed-off-by: Peng Fan <[email protected]>
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TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
# Conflicts:
# drivers/ddr/altera/Makefile
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In theory, for the same vendor, we should use the same instructions as
the spi-nor-core implementation.
Fixes: 72151ad10f8d ("mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte")
Fixes: 5bf3f3dd11db ("mtd: spi-nor: Enable QE bit for ISSI flash")
Signed-off-by: Shiji Yang <[email protected]>
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These chips are internally made of two/four dies with linear addressing
capabilities to make it transparent to the user that two/four dies were
used. There is one drawback however, the read status operation is racy
as the status bit only gives the active die status and not the status of
the other die. For commands affecting the two dies, it means if another
command is sent too fast after the first die has returned a valid
status (deviation can be up to 200us), the chip will get corrupted/in an
unstable state.
The solution adopted here is to iterate manually over all internal
dies (which takes about 30us per die) until all are ready. This approach
will always be faster than a blind delay which represents the maximum
deviation, while also being totally safe.
A flash-specific hook for the status register read had to be
implemented. Testing with the flash_speed benchmark in Linux shown no
difference with the existing performances (using the regular status read
core function).
As the presence of multiple dies is not filled in these chips SFDP
tables (the table containing the crucial information is optional), we
need to manually wire the hook.
This change is adapted from Linux.
Link: https://lore.kernel.org/all/20250110-winbond-6-12-rc1-nor-volatile-bit-v3-1-735363f8cc7d@bootlin.com/
Signed-off-by: Miquel Raynal <[email protected]>
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Some Winbond Flash chips share the same device ID. Names are not that
important for the SPI Flash, hence we don't need these duplicate ID
definitions. And the Flash size of w25q512jv is actually wrong. Clean
them up to keep the source file tidy.
Signed-off-by: Shiji Yang <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 features for the 2026.04 cycle:
This small fixes set includes fixing 64 bit builds and some warnings for
the at91 serial driver, and some cleanup on the nand driver.
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Mikhail Kshevetskiy <[email protected]> says:
It was noted that a GPT partition with the maximum available partition
number (ex: /dev/mmcblk128) can't be read/write from U-Boot using
read/write commands. Futher investigation shows that the problem is
deeper.
This set of patches fixes uncovered issues.
Link: https://lore.kernel.org/r/[email protected]
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mtdpart internally enumerate partitions starting from zero, but partition
driver API enumerate partitions starting from 1, so wrong partition will
be queried. This is wrong.
Unnecessary debug message also was removed.
Fixes: c29a6daec184 ("disk: support MTD partitions")
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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According to commit 84a42ae36683 ("dm: core: Rename device node to indicate it is private")
node_ should not be aaccess outside driver model.
Signed-off-by: Andy Yan <[email protected]>
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The H6/H616 boot ROM doesn't expect a SPL scrambled the same way as
older SoCs.
It doesn't use a specific seeds table, it expects a maximized ECC
(BCH-80), a specific BBM (FF000301) and doesn't work if empty pages are
skipped (it needs its specific BBM, even in the padding).
So, add a --soc=h6 option to support H6/616 with:
- more ECC strengths
- specific BBM
- default_scrambler_seeds[] with all values
- no empty pages skip
In Kconfig, select BCH-80 by default for SUNXI_SPL_ECC_STRENGTH to make
BROM happy.
And in scripts/Makefile.xpl, use --soc=h6 option when building for a
SUN50I_GEN_H6 SoC.
Tested on Whatsminer H616 board, booting from NAND.
Reviewed-by: Miquel Raynal <[email protected]>
Co-developed-by: James Hilliard <[email protected]>
Signed-off-by: James Hilliard <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The MACRO NFC_PAGE_SHIFT(x) already deals with removing 10 from
nand->page_shift, so it shouldn't be done twice.
Fixes: 4ccae81cdadc ("mtd: nand: Add the sunxi NAND controller driver")
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Fix a cast to pointer from integer warning on ARM64
On 64bits platform, the casts done in {read,write}l() give that kind of
warnings:
drivers/mtd/nand/raw/sunxi_nand_spl.c: In function ‘check_value_inner’:
./arch/arm/include/asm/io.h:110:43: warning: cast to pointer from \
integer of different size [-Wint-to-pointer-cast]
110 | #define __raw_readl(a) (*(volatile unsigned int *)(a))
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[...]
drivers/mtd/nand/raw/sunxi_nand_spl.c:81:27: note: in expansion of \
macro ‘readl’
81 | int val = readl(offset) & expected_bits;
Introduce {read,write}l_nfc inline function to do the right cast and
push the base address (SUNXI_NFC_BASE) into those functions, making the
code more readable.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce H6/H616 NAND controller support for SPL
The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.
For SPL, most of the work was setting the clocks, adding the new
capability structure for H616 and supporting the new USER_DATA_LEN
registers.
Tested on Whatsminer H616 board (with and without scrambling, ECC)
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce H6/H616 NAND controller support for U-Boot
The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.
Introduce the basic support, with ECC and scrambling, but without
DMA/MDMA.
Tested on Whatsminer H616 board (with and without scrambling, ECC)
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Use generic macros for ECC_MODE and RANDOM_SEED
As H6/H616 registers are different, use more generic macros than hard
coded values specific to A10-like SoC.
No functional changes.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Increase max_oobsize to take into account bigger OOB on 2KiB pages
Some NAND chip (e.g. Kioxia TC58NVG1S3HTA00) have a 2KiB page size +
128 bytes OOB.
In order to detect them, the max_oobsize has to be increased from 64 to
128 bytes.
Tested on Kioxia TC58NVG1S3HTA00 NAND chip on Whatsminer H616 board.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Use defines instead of hardcoded values for NFC_ECC_{ERR_MSK,PAT_FOUND}
SPL is using hard coded values for ECC error detection and empty chunk
detection.
The H6/H616 registers for that have changed, the pattern found is no
more in the NFC_REG_ECC_ST register.
So, don't presume anymore that pattern_found is in NFC_REG_ECC_ST, and
read the pattern_found register to get this information.
Apart from an additional register reading, no functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce NDFC Spare Area Register offset in SoC capabilities
The H6/H616 spare area register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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NFC_RANDOM_{EN,DIRECTION} registers offset moved in H616
Let's make it a SoC capability.
NFC_RANDOM_DIRECTION also moved, but it's unused, just remove it.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce per SoC capabilities in sunxi_nand_spl.c
Prepare for the H616 support that has quite a lot of differences in
registers offset and capabilities.
Start with the 512 bytes ECC capability.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce NDFC Pattern ID Register in capability structure
The H6/H616 pattern ID register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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NFC_ECC_MODE register offset moved in H616, so let's make it a SoC cap
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce has_ecc_block_512 capability
The H616 controller can't handle 512 bytes ECC block size. The
NFC_ECC_BLOCK_512 bit disappeared in H6, and NDFC_RANDOM_EN took its
place.
So, add has_ecc_block_512 capability to only set this bit on SoC having
it.
On the way, let's drop NFC_ECC_BLOCK_SIZE_MSK which was just a mask for
the very same bit.
No functional change.
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Move ECC_PAT_FOUND register in SoC capabilities structure
This register offset moved in H616, it's now its own register (@0x3c,
bits 0-31), not shared with NFC_ECC_ST any more (was @0x38 bits 16-31).
Push that specificity in caps structure.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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USER_DATA register offset moved in H616, so let's make it a SoC cap
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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ECC_ERR_CNT register offset moved in H616, so let's make it a SoC cap
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce per SoC capabilities in sunxi_nand.c
This prepares for the H616 support that has quite a lot differences in
registers offset and capabilities.
Start with the ECC strength table.
No functional change.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Merge common register definitions from sunxi_nand{,_spl}.c
The Allwinner NAND controller registers where in both files, so let's
just merge all that in a header, it will be easier for maintenance.
NB: the defines are also harmonized with Linux driver
No functional change
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The sunxi_ccm_reg is legacy, drop its usage from nand related code
For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock
files when missing.
And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the
new scheme.
Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N
Suggested-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Remove unneeded definitions NFC_CMD_R* in sunxi_nand_spl.c
No need to define NFC_CMD_RNDOUTSTART, NFC_CMD_RNDOUT and
NFC_CMD_READSTART here since they are already in linux/mtd/rawnand.h
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Harmonize registers definition in sunxi_nand{,_spl}.c files
This is a first step to then include the same file from both
sunxi_nand{,_spl}.c files
Unused defines are also removed
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Fix pointer from interget warning when compiling for ARM64
When compiling for arm64, we get this error:
error: passing argument 2 of ‘__memcpy_fromio’ makes pointer from
integer without a cast [-Wint-conversion]
Moreover the copy should be made with dedicated readl(), like for any
register access on this peripheral, since they are 32bit wide.
So, instead of memcpy_fromio(), just use a readl() loop.
Introduce nand_readlcpy() to implement this loop.
Fixes: 6ddbb1e936c7 ("spl: nand: sunxi: use PIO instead of DMA")
Suggested-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Remove 'complete' member from struct sunxi_nfc
The 'complete' member isn't part of the structure, let's remove it.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Prepare v2026.01-rc4
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The ALTERA_QSPI driver conflicts with the regular FLASH_CFI_DRIVER as
both implement the same high level functionality and so use the same
global namespace. In a similar fashion, all NAND drivers are mutually
exclusive due to namespace collisions. For the remaining drivers which
did not already have some architecture specific dependency, add them.
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2026.01 cycle:
This small fixes set includes a fix on the mtd pmecc driver.
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Enable ONFI parameter page detection for SoCFPGA SoC64 devices by
selecting SYS_NAND_ONFI_DETECTION in the NAND_DENALI Kconfig entry.
This allows SoCFPGA SoC64 platforms using the Denali NAND controller
to automatically detect NAND parameters via the ONFI interface instead
of relying on hardcoded configuration values.
The selection is limited to TARGET_SOCFPGA_SOC64 to avoid affecting
non-SoC64 platforms that use legacy NAND handling.
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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"timing" and "timing_res_idx" are unused and not exist in Linux driver,
let's remove them.
Signed-off-by: Zixun LI <[email protected]>
Acked-by: Alexander Dahl <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
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Setup the pmecc data setup time as 3 clock cycles for 133MHz as
recommended by the datasheet.
Backported from Linux: f55f552a7c7e0a1 ("mtd: rawnand: atmel: set pmecc
data setup time")
Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver")
Signed-off-by: Zixun LI <[email protected]>
Tested-by: Alexander Dahl <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
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This option is only meaningful within the davinci nand driver, so drop
the statement here (which had no effect).
Signed-off-by: Tom Rini <[email protected]>
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Add support for FudanMicro FM25S01A SPI NAND.
This driver is ported from linux v6.18 and tested on a MT7981 board.
Link: https://lore.kernel.org/linux-mtd/[email protected]/
Reviewed-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
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The hidden symbol SPL_SYS_NAND_SELF_INIT was not being used correctly
leading to Kconfig dependency issues seen with "make allyesconfig". As
it's a select'd symbol we don't need to have a depends line on it, and
then in turn we need to also update the logic on SYS_NAND_PAGE_SIZE and
SYS_NAND_OOBSIZE.
Signed-off-by: Tom Rini <[email protected]>
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All these chips are dual and quad capable. They are also DTR capable,
but the core is not yet ready for that.
Performances of all chips are comparable at 30MHz and are as follow:
Eraseblock single read speed: 938kiB/s
Eraseblock dual read speed: 1068kiB/s
Eraseblock quad read speed: 3751kiB/s
Signed-off-by: Miquel Raynal <[email protected]>
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When printing the contents of an lbaint_t variable we need to use LBAF
to print it in order to get the correct format type depending on 32 or
64bit-ness.
Signed-off-by: Tom Rini <[email protected]>
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When printing the contents of an size_t variable we need to use z prefix
to the format character in order to get the correct format type
depending on 32 or 64bit-ness.
Signed-off-by: Tom Rini <[email protected]>
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This feature requires that CFG_SYS_FLASH_BASE is defined and this in
turn is only done in the case of FLASH_CFI_DRIVER && !CFI_FLASH or in
other words, when DM_MTD is not enabled.
Signed-off-by: Tom Rini <[email protected]>
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