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2026-05-01mtd: nand: raw: sunxi_spl: remove user data length resetRichard Genoud
No need to reset user data length registers in SPL. In SPL, only the first user data length register is used, so we don't need to reset all of them. Signed-off-by: Richard Genoud <[email protected]> Acked-by: Andre Przywara <[email protected]>
2026-05-01mtd: rawnand: sunxi: introduce variable user data lengthRichard Genoud
In Allwinner SoCs, user data can be added in OOB before each ECC data. For older SoCs like A10, the user data size was the size of a register (4 bytes) and was mandatory before each ECC step. So, the A10 OOB Layout is: [4Bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [4bytes USER_DATA_STEP1] [ECC_STEP1 bytes] ... NB: the BBM is stored at the beginning of the USER_DATA_STEP0. Now, for H6/H616 NAND flash controller, this user data can have a different size for each step. So, we are maximizing the user data length to use as many OOB bytes as possible. Fixes: 7d1de9801151 ("mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller") Fixes: f163da5e6d26 ("mtd: rawnand: sunxi: add support for H6/H616 nand controller") Signed-off-by: Richard Genoud <[email protected]>
2026-05-01mtd: rawnand: sunxi: clean sunxi_nand_chip_init()Richard Genoud
In sunxi_nand_chip_init there's quite a lot of kfree/return, it's easy to forget a kfree(), so use a goto/kfree instead. Signed-off-by: Richard Genoud <[email protected]> [Andre: rename goto label, keep return 0;] Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2026-05-01mtd: rawnand: sunxi: make the code mode self-explanatoryRichard Genoud
In sunxi_nfc_hw_ecc_{read,write}_chunk(), the ECC step was force to 0, the reason is not trivial to get when reading the code. The explanation is that, from the NAND flash controller perspective, we are indeed at step 0 for user data length and ECC errors. Just add a const value with an explanation to clarify things. Signed-off-by: Richard Genoud <[email protected]> Reviewed-By: Michael Trimarchi <[email protected]> Acked-by: Andre Przywara <[email protected]>
2026-05-01mtd: rawnand: sunxi: Replace hard coded value by a defineRichard Genoud
The user data length (4) used all over the code hard coded. And sometimes, it's not that trivial to know that it's the user data length and not something else. Moreover, for the H6/H616 this value is no more fixed by hardware, but could be modified. Using a define here makes the code more readable. Suggested-by: Miquel Raynal <[email protected]> Reviewed-by: Michael Trimarchi <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Acked-by: Andre Przywara <[email protected]>
2026-04-15mtd: spi-nor-ids: add flags for mx25u12835fDavid Lechner
Add some capability flags for mx25u12835f. In particular, we are interested in using the lock feature. According to the datasheet, dual/quad read is also supported. Signed-off-by: David Lechner <[email protected]>
2026-04-15spi: Correct dependencies for SPI_FLASH_SSTTom Rini
The SPI_FLASH_SST functionality is a subset of SPI_FLASH_LOCK today, so express this dependency in Kconfig. Signed-off-by: Tom Rini <[email protected]>
2026-04-15mtd: spi-nor: Add is25wx128 and is25lx128 chipsFlaviu Nistor
Add is25wx128 and is25lx128 ISSI chips to spi-nor id table. Both chips have a size of 16MB but is25wx128 is the 1.8V version and is25lx128 is the 3v version. Signed-off-by: Flaviu Nistor <[email protected]>
2026-04-15mtd: spi-nor-ids: Add support for IS25WP01GG SPI NOR flashChen Huei Lok
Add a new entry for the IS25WP01GG SPI NOR flash (ID 0x9d7021, 64KB sectors, 2KB page size) with 4K sectors, dual and quad read support. This flash is used and tested on N5X boards. Datasheet : https://www.issi.com/WW/pdf/25LP-WP01GG.pdf Signed-off-by: Chen Huei Lok <[email protected]>
2026-04-15mtd: spi-nor: Add gd25lx128j chipFlaviu Nistor
Add gd25lx128j GIGADEVICE chip to spi-nor id table. Signed-off-by: Flaviu Nistor <[email protected]>
2026-04-15mtd: spi-nor: ids: add ISSI IS25LP*J/*MJ/*E and IS25WP*J/*MJ device IDsJeffrey Yu
Add JEDEC ID table entries for additional ISSI SPI-NOR devices. These parts previously not yet supported. With these entries, U-Boot can match the device by JEDEC ID and use the existing ISSI SPI-NOR device handling. Newly added devices include: - IS25LP512MJ (JEDEC 0x9d6020) https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf - IS25WP512MJ (JEDEC 0x9d7020) https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf - IS25LP010E (JEDEC 0x9d4011) https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf - IS25LP020E (JEDEC 0x9d4012) https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf - IS25LP040E (JEDEC 0x9d4013) https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf - IS25LP01GJ (JEDEC 0x9d6021) https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf - IS25LP02GG (JEDEC 0x9d6022) https://www.issi.com/WW/pdf/25LP-WP02GG.pdf - IS25LP02GJ (JEDEC 0x9d6022) https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf - IS25WP01GG (JEDEC 0x9d7021) https://www.issi.com/WW/pdf/25LP-WP01GG.pdf - IS25WP01GJ (JEDEC 0x9d7021) https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf - IS25WJ128F (JEDEC 0x9d7118) https://www.issi.com/WW/pdf/25WJ128F.pdf - IS25WP02GG (JEDEC 0x9d7022) https://www.issi.com/WW/pdf/25LP-WP02GG.pdf - IS25WP02GJ (JEDEC 0x9d7022) https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf Signed-off-by: jeffrey yu <[email protected]> [trini: Fix spacing issues] Signed-off-by: Tom Rini <[email protected]>
2026-04-15mtd: spi-nor: Add Dosilicon DS25M/Q series supportSsunk
Add support for dosilicon ds25m4cb, ds25m4dn, ds25q4cb, ds25q4dn Datasheets: ds25m4cb: https://www.dosilicon.com/resources/SPI%20NOR/DS25M4CB-XXXXX_Rev04.pdf ds25m4dn: https://www.dosilicon.com/resources/SPI%20NOR/DS25M4DN-XXXXX_Rev03.pdf ds25q4cb: https://www.dosilicon.com/resources/SPI%20NOR/DS25Q4CB-XXXXX_Rev03.pdf ds25q4dn: https://www.dosilicon.com/resources/SPI%20NOR/DS25Q4DN-XXXXX_Rev01.pdf Signed-off-by: Ssunk <[email protected]> [trini: Adjust spacing] Signed-off-by: Tom Rini <[email protected]>
2026-04-15mtd: spi: spi-nor-ids: Add support for XMC XM25QH01DSsunk
Add support for XMC XM25QH01D SPI NOR flash. Datasheet: https://www.xmcwh.com/uploads/958/XM25QH01D_Ver1.0.pdf Link: https://lore.kernel.org/u-boot/[email protected]/
2026-04-15mtd: spi-nor: ids: Add support for Puyasemi flash chipsSsunk
Add JEDEC IDs for Puyasemi PY25F512HB, PY25F01GHB, PY25F512LC, and PY25F01GLC flash parts. Datasheets: PY25F512HB: https://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash%20%E8%8A%AF%E7%89%87/PY25F512HB_Datasheet_V1.2.pdf PY25F01GHB: https://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25F01GHB_Datasheet_V1.1.pdf PY25F512LC: https://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/PY25F512LC_Datasheet_V1.3.pdf PY25F01GLC: https://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash%20%E8%8A%AF%E7%89%87/PY25F01GLC_Datasheet_V1.0.pdf Reviewed-by: Anshul Dalal <[email protected]> Signed-off-by: Ssunk <[email protected]>
2026-02-20spi: add support for ISSI IS25WP02GG flashJeffrey Yu
This patch adds support for the ISSI IS25WP02GG QSPI NOR flash device. Tested on the Versal VMK180 board in dual-parallel QSPI configuration. Signed-off-by: jeffrey yu <[email protected]>
2026-02-20mtd: spi-nor-ids: Add Fujitsu MB85RS256TY FRAMChristoph Reiter
This part is an FRAM, but can be used through the spi-nor generic code. Signed-off-by: [email protected]
2026-02-17Merge patch series "treewide: Clean up usage of DECLARE_GLOBAL_DATA_PTR"Tom Rini
Peng Fan (OSS) <[email protected]> says: This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR instances. Many files declare DECLARE_GLOBAL_DATA_PTR and include asm/global_data.h even though gd is never used. In these cases, asm/global_data.h is effectively treated as a proxy header, which is not a good practice. Following the Include What You Use principle, files should include only the headers they actually depend on, rather than relying on global_data.h indirectly. This approach is also adopted in Linux kernel [1]. The first few patches are prepartion to avoid building break after remove the including of global_data.h. A script is for filtering the files: list=`find . -name "*.[ch]"` for source in ${list} do result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}` if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then echo "Found in ${source}" result=`sed -n '/\<gd\>/p' ${source}` result2=`sed -n '/\<gd_/p' ${source}` result3=`sed -n '/\<gd->/p' ${source}` if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then echo "Cleanup ${source}" sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source} sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source} sed -i '/global_data.h/d' ${source} git add ${source} fi fi done [1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf CI: https://github.com/u-boot/u-boot/pull/865 Link: https://lore.kernel.org/r/[email protected]
2026-02-17treewide: Clean up DECLARE_GLOBAL_DATA_PTR usagePeng Fan
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and drop the unnecessary inclusion of asm/global_data.h. Headers should be included directly by the files that need them, rather than indirectly via global_data.h. Reviewed-by: Patrice Chotard <[email protected]> #STMicroelectronics boards and STM32MP1 ram test driver Tested-by: Anshul Dalal <[email protected]> #TI boards Acked-by: Yao Zi <[email protected]> #TH1520 Signed-off-by: Peng Fan <[email protected]>
2026-02-14Replace TARGET namespace and cleanup properlyTien Fong Chee
TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]> # Conflicts: # drivers/ddr/altera/Makefile
2026-02-13mtd: spi-nor-tiny: fix 4-Byte address instructions for Cypress and ISSIShiji Yang
In theory, for the same vendor, we should use the same instructions as the spi-nor-core implementation. Fixes: 72151ad10f8d ("mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte") Fixes: 5bf3f3dd11db ("mtd: spi-nor: Enable QE bit for ISSI flash") Signed-off-by: Shiji Yang <[email protected]>
2026-02-13mtd: spi-nor: winbond: Make sure w25q{01, 02}jv behave correctlyMiquel Raynal
These chips are internally made of two/four dies with linear addressing capabilities to make it transparent to the user that two/four dies were used. There is one drawback however, the read status operation is racy as the status bit only gives the active die status and not the status of the other die. For commands affecting the two dies, it means if another command is sent too fast after the first die has returned a valid status (deviation can be up to 200us), the chip will get corrupted/in an unstable state. The solution adopted here is to iterate manually over all internal dies (which takes about 30us per die) until all are ready. This approach will always be faster than a blind delay which represents the maximum deviation, while also being totally safe. A flash-specific hook for the status register read had to be implemented. Testing with the flash_speed benchmark in Linux shown no difference with the existing performances (using the regular status read core function). As the presence of multiple dies is not filled in these chips SFDP tables (the table containing the crucial information is optional), we need to manually wire the hook. This change is adapted from Linux. Link: https://lore.kernel.org/all/20250110-winbond-6-12-rc1-nor-volatile-bit-v3-1-735363f8cc7d@bootlin.com/ Signed-off-by: Miquel Raynal <[email protected]>
2026-02-13mtd: spi-nor-ids: remove duplicate IDs for w25q32 and w25q512 seriesShiji Yang
Some Winbond Flash chips share the same device ID. Names are not that important for the SPI Flash, hence we don't need these duplicate ID definitions. And the Flash size of w25q512jv is actually wrong. Clean them up to keep the source file tidy. Signed-off-by: Shiji Yang <[email protected]>
2026-02-08Merge tag 'u-boot-at91-2026.04-a' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-at91 features for the 2026.04 cycle: This small fixes set includes fixing 64 bit builds and some warnings for the at91 serial driver, and some cleanup on the nand driver.
2026-02-04Merge patch series "part: fix partition searching"Tom Rini
Mikhail Kshevetskiy <[email protected]> says: It was noted that a GPT partition with the maximum available partition number (ex: /dev/mmcblk128) can't be read/write from U-Boot using read/write commands. Futher investigation shows that the problem is deeper. This set of patches fixes uncovered issues. Link: https://lore.kernel.org/r/[email protected]
2026-02-04mtd: mtdpart: fix partitions searchingMikhail Kshevetskiy
mtdpart internally enumerate partitions starting from zero, but partition driver API enumerate partitions starting from 1, so wrong partition will be queried. This is wrong. Unnecessary debug message also was removed. Fixes: c29a6daec184 ("disk: support MTD partitions") Signed-off-by: Mikhail Kshevetskiy <[email protected]>
2026-02-04mtd: nand: raw: atmel: Access device ofnode through functionsAndy Yan
According to commit 84a42ae36683 ("dm: core: Rename device node to indicate it is private") node_ should not be aaccess outside driver model. Signed-off-by: Andy Yan <[email protected]>
2026-02-03tools: sunxi-spl-image-builder: support H6/H616 NAND bootRichard Genoud
The H6/H616 boot ROM doesn't expect a SPL scrambled the same way as older SoCs. It doesn't use a specific seeds table, it expects a maximized ECC (BCH-80), a specific BBM (FF000301) and doesn't work if empty pages are skipped (it needs its specific BBM, even in the padding). So, add a --soc=h6 option to support H6/616 with: - more ECC strengths - specific BBM - default_scrambler_seeds[] with all values - no empty pages skip In Kconfig, select BCH-80 by default for SUNXI_SPL_ECC_STRENGTH to make BROM happy. And in scripts/Makefile.xpl, use --soc=h6 option when building for a SUN50I_GEN_H6 SoC. Tested on Whatsminer H616 board, booting from NAND. Reviewed-by: Miquel Raynal <[email protected]> Co-developed-by: James Hilliard <[email protected]> Signed-off-by: James Hilliard <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: fix page size in control registerRichard Genoud
The MACRO NFC_PAGE_SHIFT(x) already deals with removing 10 from nand->page_shift, so it shouldn't be done twice. Fixes: 4ccae81cdadc ("mtd: nand: Add the sunxi NAND controller driver") Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: Fix cast to pointer from integer warningsRichard Genoud
Fix a cast to pointer from integer warning on ARM64 On 64bits platform, the casts done in {read,write}l() give that kind of warnings: drivers/mtd/nand/raw/sunxi_nand_spl.c: In function ‘check_value_inner’: ./arch/arm/include/asm/io.h:110:43: warning: cast to pointer from \ integer of different size [-Wint-to-pointer-cast] 110 | #define __raw_readl(a) (*(volatile unsigned int *)(a)) | ^ [...] drivers/mtd/nand/raw/sunxi_nand_spl.c:81:27: note: in expansion of \ macro ‘readl’ 81 | int val = readl(offset) & expected_bits; Introduce {read,write}l_nfc inline function to do the right cast and push the base address (SUNXI_NFC_BASE) into those functions, making the code more readable. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: add support for H6/H616 nand controllerRichard Genoud
Introduce H6/H616 NAND controller support for SPL The H616 NAND controller has the same base as A10/A23, with some differences: - MDMA is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. For SPL, most of the work was setting the clocks, adding the new capability structure for H616 and supporting the new USER_DATA_LEN registers. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: add support for H6/H616 nand controllerRichard Genoud
Introduce H6/H616 NAND controller support for U-Boot The H616 NAND controller has the same base as A10/A23, with some differences: - MDMA is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. Introduce the basic support, with ECC and scrambling, but without DMA/MDMA. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: use NFC_ECC_MODE and NFC_RANDOM_SEED macrosRichard Genoud
Use generic macros for ECC_MODE and RANDOM_SEED As H6/H616 registers are different, use more generic macros than hard coded values specific to A10-like SoC. No functional changes. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: increase max_oobsize for 2KiB pagesRichard Genoud
Increase max_oobsize to take into account bigger OOB on 2KiB pages Some NAND chip (e.g. Kioxia TC58NVG1S3HTA00) have a 2KiB page size + 128 bytes OOB. In order to detect them, the max_oobsize has to be increased from 64 to 128 bytes. Tested on Kioxia TC58NVG1S3HTA00 NAND chip on Whatsminer H616 board. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: use NFC_ECC_ERR_MSK and NFC_ECC_PAT_FOUNDRichard Genoud
Use defines instead of hardcoded values for NFC_ECC_{ERR_MSK,PAT_FOUND} SPL is using hard coded values for ECC error detection and empty chunk detection. The H6/H616 registers for that have changed, the pattern found is no more in the NFC_REG_ECC_ST register. So, don't presume anymore that pattern_found is in NFC_REG_ECC_ST, and read the pattern_found register to get this information. Apart from an additional register reading, no functional change. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: introduce reg_spare_area in sunxi_nfc_capsRichard Genoud
Introduce NDFC Spare Area Register offset in SoC capabilities The H6/H616 spare area register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: move NFC_RANDOM_EN register offset in SoC capsRichard Genoud
NFC_RANDOM_{EN,DIRECTION} registers offset moved in H616 Let's make it a SoC capability. NFC_RANDOM_DIRECTION also moved, but it's unused, just remove it. No functional change. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: add per SoC capabilitiesRichard Genoud
Introduce per SoC capabilities in sunxi_nand_spl.c Prepare for the H616 support that has quite a lot of differences in registers offset and capabilities. Start with the 512 bytes ECC capability. No functional change. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: introduce reg_pat_id in sunxi_nfc_capsRichard Genoud
Introduce NDFC Pattern ID Register in capability structure The H6/H616 pattern ID register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: move NFC_ECC_MODE offset in SoC capsRichard Genoud
NFC_ECC_MODE register offset moved in H616, so let's make it a SoC cap No functional change. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: add has_ecc_block_512 capabilityRichard Genoud
Introduce has_ecc_block_512 capability The H616 controller can't handle 512 bytes ECC block size. The NFC_ECC_BLOCK_512 bit disappeared in H6, and NDFC_RANDOM_EN took its place. So, add has_ecc_block_512 capability to only set this bit on SoC having it. On the way, let's drop NFC_ECC_BLOCK_SIZE_MSK which was just a mask for the very same bit. No functional change. Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: move ECC_PAT_FOUND register in SoC capsRichard Genoud
Move ECC_PAT_FOUND register in SoC capabilities structure This register offset moved in H616, it's now its own register (@0x3c, bits 0-31), not shared with NFC_ECC_ST any more (was @0x38 bits 16-31). Push that specificity in caps structure. Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: move USER_DATA register offset in SoC capsRichard Genoud
USER_DATA register offset moved in H616, so let's make it a SoC cap Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: move ECC_ERR_CNT register offset in SoC capsRichard Genoud
ECC_ERR_CNT register offset moved in H616, so let's make it a SoC cap Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: add per SoC capabilitiesRichard Genoud
Introduce per SoC capabilities in sunxi_nand.c This prepares for the H616 support that has quite a lot differences in registers offset and capabilities. Start with the ECC strength table. No functional change. Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: merge register definitions for sunxi_nand{, _spl}.cRichard Genoud
Merge common register definitions from sunxi_nand{,_spl}.c The Allwinner NAND controller registers where in both files, so let's just merge all that in a header, it will be easier for maintenance. NB: the defines are also harmonized with Linux driver No functional change Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: remove usage of struct sunxi_ccm_regRichard Genoud
The sunxi_ccm_reg is legacy, drop its usage from nand related code For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock files when missing. And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the new scheme. Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N Suggested-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: cosmetic: use definitions from linux/mtd/rawnand.hRichard Genoud
Remove unneeded definitions NFC_CMD_R* in sunxi_nand_spl.c No need to define NFC_CMD_RNDOUTSTART, NFC_CMD_RNDOUT and NFC_CMD_READSTART here since they are already in linux/mtd/rawnand.h Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: harmonize register defines with non spl fileRichard Genoud
Harmonize registers definition in sunxi_nand{,_spl}.c files This is a first step to then include the same file from both sunxi_nand{,_spl}.c files Unused defines are also removed Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi_spl: fix pointer from integer without a castRichard Genoud
Fix pointer from interget warning when compiling for ARM64 When compiling for arm64, we get this error: error: passing argument 2 of ‘__memcpy_fromio’ makes pointer from integer without a cast [-Wint-conversion] Moreover the copy should be made with dedicated readl(), like for any register access on this peripheral, since they are 32bit wide. So, instead of memcpy_fromio(), just use a readl() loop. Introduce nand_readlcpy() to implement this loop. Fixes: 6ddbb1e936c7 ("spl: nand: sunxi: use PIO instead of DMA") Suggested-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
2026-02-03mtd: rawnand: sunxi: cosmetic: remove needless commentRichard Genoud
Remove 'complete' member from struct sunxi_nfc The 'complete' member isn't part of the structure, let's remove it. Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-27 12:06:28 +0000