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Signed-off-by: Tom Rini <[email protected]>
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Adapt behaviour to Linux kernel driver.
The return value of gpio_request_by_name_nodev() was not checked before,
and thus in case 'rb-gpios' was missing in DT, rb.type was set to
ATMEL_NAND_GPIO_RB nevertheless, leading to output like this for
example (on sam9x60-curiosity with the line removed from dts):
NAND: Could not find valid ONFI parameter page; aborting
device found, Manufacturer ID: 0xc2, Chip ID: 0xdc
Macronix NAND 512MiB 3,3V 8-bit
512 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 64
atmel-nand-controller nand-controller: NAND scan failed: -22
Failed to probe nand driver (err = -22)
Failed to initialize NAND controller. (error -22)
0 MiB
Note: not having that gpio assigned in dts is possible, the driver does
not override nand_chip->dev_ready() then and a generic solution is used.
Fixes: 6a8dfd57220d ("nand: atmel: Add DM based NAND driver")
Signed-off-by: Alexander Dahl <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
Acked-by: Michael Trimarchi <[email protected]>
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This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <[email protected]>
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This patch adds support for the MX25U25635F QSPI Flash Memory.
Signed-off-by: Neal Frager <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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The last user of the NEEDS_MANUAL_RELOC has been removed in commit
26af162ac8f8 ("arch: m68k: Implement relocation")
Remove now unused NEEDS_MANUAL_RELOC code.
Signed-off-by: Marek Vasut <[email protected]>
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The sandbox_set_enable_memio() should only ever be set during
sandbox testing, not within driver itself, move it back to test/ .
Signed-off-by: Marek Vasut <[email protected]>
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64bit systems
Cast the address such that it can be printed without warnings
on both 32bit and 64bit systems. This really should use some
better print formatter, but for the lack of it, do it this way.
Signed-off-by: Marek Vasut <[email protected]>
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Get rid of nvmxip_mmio_rawread() and just implement the readl()/readq()
reader loop within nvmxip_blk_read(). Cast the destination buffer as
needed and increment the read by either 4 or 8 bytes depending on if
this is systemd with 32bit or 64bit physical address.
Signed-off-by: Marek Vasut <[email protected]>
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Perform all the block device creation only once, after the driver itself
successfully bound. Do not do this in uclass post bind, as this might be
triggered multiple times. For example the ut_dm_host test triggers this
and triggers a memory leak that way, since there are now multiple block
devices created using the blk_create_devicef() .
To retain the old probe-on-boot behavior, set DM_FLAG_PROBE_AFTER_BIND
flag in uclass post_bind callback, so the driver model would probe the
driver at the right time.
Rename the function as well, to match similar functions in
other block-related subsystems, like the mmc one.
Signed-off-by: Marek Vasut <[email protected]>
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Signed-off-by: Alexander Dahl <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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Rockchip boot blocks are written per 4 x 512 byte sectors per page.
Each page must have a page address (PA) pointer in OOB to the next page.
Pages are written in a pattern depending on the NAND chip ID.
This logic used to build a page pattern table is not fully disclosed and
is not easy to fit in the MTD framework.
The formula in rk_nfc_write_page_hwecc() function is not correct.
Make hwecc and raw behavior identical.
Generate boot block page address and pattern for hwecc in user space
and copy PA data to/from the already reserved last 4 bytes before EEC
in the chip->oob_poi data layout.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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cfi_mtd requires add_mtd_device() which is available only when MTD is
enabled that's why record this dependency.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com
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status and ecc_status are of unsigned type where they are compared for
negative value. This is pointed by below sparse warning. Change datatype
to int to fix this.
warning: comparison of unsigned expression in '< 0' is always false
[-Wtype-limits]
Signed-off-by: Algapally Santosh Sagar <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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- Add xtxtech spi-nor chip parts (Bruce Suen)
- Add bcm63xx-hsspi driver fixes (William Zhang)
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Add support for Winbond 256M-bit flash w25q256jwm.
Performed basic erase/write/readback operations on
ZynqMP zc1751+dc1 board.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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add following XTX part numbers to the list:
xt25f08: 3V QSPI, 8Mbit
xt25f16: 3V QSPI, 16Mbit
xt25f32: 3V QSPI, 32Mbit
xt25f64: 3V QSPI, 64Mbit
xt25f128: 3V QSPI, 128Mbit
xt25f256: 3V QSPI, 256Mbit
xt25q08: 1.8V QSPI, 8Mbit
xt25q16: 1.8V QSPI, 16Mbit
xt25q32: 1.8V QSPI, 32Mbit
xt25q64: 1.8V QSPI, 64Mbit
xt25q128: 1.8V QSPI, 128Mbit
xt25q256: 1.8V QSPI, 256Mbit
xt25q512: 1.8V QSPI, 512Mbit
xt25q01g: 1.8V QSPI, 1Gbit
xt25w512: wide voltage, QSPI, 512Mbit
xt25w01g: wide voltage, QSPI, 1Gbit
remove xt25f128b and add xt25f128,because xt25f128b andxt25f128f
share same jdec id,we use xt25f128 instead.
Signed-off-by: Bruce Suen <[email protected]>
[jagan: re-edited the entire patch]
Signed-off-by: Jagan Teki <[email protected]>
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XTX changed full company name from "XTX Technology (Shenzhen) Limited
to "XTX Technology Limited" since 2020,So remove "(Shenzhen)".
Signed-off-by: Bruce Suen <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and
a generic local bus controller (Device Bus Controller) that share common
pins.
With a board design that incorporates both a NAND flash and uses
the Device Bus (in our case for an SRAM) accessing the Device Bus device
fails unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Move header to include to allow external code
to get the internal bdev structures to access
block device operations.
as at it, just add the UCLASS_NVMXIP string
so we get the correct output in partitions
listing.
Signed-off-by: Rui Miguel Silva <[email protected]>
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Use proper project name in comments, Kconfig, readmes.
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Qu Wenruo <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
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flash_get_size() will get the flash size from the device itself and go
through all erase regions to read protection status. However, the device
mappable region (eg: devicetree reg property) might be lower than the
device full size which means that the above cycle will result in a data
bus exception. This change fixes it by reading the 'addr_size' during
probe() and also use that as one possible upper limit.
Signed-off-by: Nuno Sá <[email protected]>
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The 'tiny' SPI nor functions have the same name as their big brothers,
which can be confusing. Use different names so it is clear which
version is in the image.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero
error. Check for this and return a proper error instead.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support
Signed-off-by: Paweł Jarosz <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Acked-by: Michael Trimarchi <[email protected]>
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The MTD framework reserves 1 or 2 bytes for the bad block marker
depending on the bus size. The rockchip_nfc driver currently only
supports a 8 bit bus, but reserves standard 2 bytes for the BBM.
The first free OOB byte is therefore OOB2 at offset 2.
Page address(PA) bytes are moved to the last 4 positions before
ECC. Update the description for U-boot.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add flash_node to the rockchip_nfc driver chip structure in order
to find the partitions in the add_mtd_partitions_of() function.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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The compatible string for rk3308 has as fallback string
"rockchip,rv1108-nfc". As there is no logic in probe priority between
the SoC orientated string and the fall back, so remove the compatible
string "rockchip,rk3308-nfc" from the driver.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip_nfc.c file.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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- cadence-quadspi fixes (Apurva Nandan, Dhruva Gole)
- CHIP_ERASE optimization (Marek Vasut)
- fixups for s25fs512s (Takahiro Kuwano)
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Please pull the second part of the sunxi pull request for this cycle.
Another bunch of patches that replace old-school U-Boot hacks with
proper DM based code, this time for the raw NAND flash driver, and the
USB PHY VBUS detection code. Plus two smaller patches that were sitting
in my inbox for a while.
Gitlab CI passed. In lack of some supported board with NAND flash I
couldn't really test this part, but apparently this was tested by the
reviewer. I briefly ran the branch on some boards with USB-OTG, and
this still worked.
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Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This more closely matches the U-Boot driver to the Linux version.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Michael Trimarchi <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Clocks, resets, and pinmuxes are now handled by the driver model, so the
only thing the "board" code needs to do is load the driver. This matches
the pattern used by other DM raw NAND drivers (there is no NAND uclass).
The actual board code is now only needed in SPL.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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As a first step toward converting this driver to the driver model, use
the ofnode abstraction to replace direct references to the FDT blob.
Using ofnode_read_u32_index removes an extra pair of loops and makes the
allwinner,rb property optional, matching the devicetree binding.
Signed-off-by: Samuel Holland <[email protected]>
Acked-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Each chip is required to have a unique CS number ("reg" property) in the
range 0-7, so there is no need to separately count the number of chips.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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enable NVMXIP QSPI for sandbox 64-bit
Adding two NVM XIP QSPI storage devices.
Signed-off-by: Abdellatif El Khlifi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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add nvmxip_qspi driver under UCLASS_NVMXIP
The device associated with this driver is the parent of the blk#<id> device
nvmxip_qspi can be reused by other platforms. If the platform
has custom settings to apply before using the flash, then the platform
can provide its own parent driver belonging to UCLASS_NVMXIP and reuse
nvmxip-blk driver. The custom driver can be implemented like nvmxip_qspi in
addition to the platform custom settings.
Platforms can use multiple NVM XIP devices at the same time by defining a
DT node for each one of them.
For more details please refer to doc/develop/driver-model/nvmxip_qspi.rst
Signed-off-by: Abdellatif El Khlifi <[email protected]>
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add block storage emulation for NVM XIP flash devices
Some paltforms such as Corstone-1000 need to see NVM XIP raw flash
as a block storage device with read only capability.
Here NVM flash devices are devices with addressable
memory (e.g: QSPI NOR flash).
The implementation is generic and can be used by different platforms.
Two drivers are provided as follows.
nvmxip-blk :
a generic block driver allowing to read from the XIP flash
nvmxip Uclass driver :
When a device is described in the DT and associated with
UCLASS_NVMXIP, the Uclass creates a block device and binds it with
the nvmxip-blk.
Platforms can use multiple NVM XIP devices at the same time by defining a
DT node for each one of them.
Signed-off-by: Abdellatif El Khlifi <[email protected]>
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This patch adds fixups for s25fs512s to address the following issues
from reading SFDP:
- Non-uniform sectors by factory default. The setting needs to be
checked and assign erase hook as needed.
- Page size is wrongly advertised in SFDP.
- READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h)
are not supported.
- Bank Address Register (BAR) is not supported.
In addition, volatile version of Quad Enable is used for safety.
Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated
to use 4-byte address commands instead of extended address mode and the
page_size is fixed to 256
For future use, manufacturer code should be moved out from framework
code as same as in Linux.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Cong Dang <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add support for CHIP_ERASE opcode 0xc7 . This is useful in case the
entire SPI NOR is supposed to be erase at once, as is it considerably
faster than 4k sector erase and even slightly faster than 64k block
erase. The spi_nor_erase_chip() implementation is adapted from Linux
6.1.y as of commit 7d54cb2c26dad ("Linux 6.1.14") . The chip erase is
only used in case the entire MTD device is being erased, and the chip
does support this functionality.
Timing figures from W25Q128JW:
16 MiB erase using 4kiB sector erase opcode 0x20 ... 107.5s
16 MiB erase using 64kiB block erase opcode 0xd8 ... 39.1s
16 MiB erase using chip erase opcode 0xc7 .......... 38.7s
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm
configs:
_ Add usb_pgood_delay for ST boards
_ increase malloc size for pre-reloc for stm32mp15
_ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15
dts:
_ Add QSPI support on STM32MP13x SoC family
_ Add FMC support on STM32MP13x SoC family
drivers/machine:
_ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
_ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
_ rawnand: stm32_fmc2: remove unsupported EDO mode
_ stm32mp: fix various array bounds checks
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For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
Reviewed-by: Michael Trimarchi <[email protected]>
Acked-by: William Zhang <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Tested-by: Tom Rini <[email protected]> [am335x_evm]
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Dario Binacchi <[email protected]>
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It will be replaced by a more recent version which contains fixes for
tests run by Tom Rini.
This reverts commit ff33d3c87c2a1ab576607c2f67a9cb7690a4e7ca.
Signed-off-by: Dario Binacchi <[email protected]>
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Remove the EDO mode support from as the FMC2 controller does not
support the feature.
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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octeontx_bch_devices and octeontx_pci_nand_deferred_devices are only
referenced in the files where they are defined. Make them static.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Michael Trimarchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Dario Binacchi <[email protected]>
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