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Add support for reading param page of NAND device.
These paramaters are unique and used for identification purpose.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Add support for readid command in Cadence NAND driver.
The id is unique and used for flash identification.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Add support for read status command
in Cadence NAND driver. This status bit is important to check
whether the flash is write-protected.
Signed-off-by: Dinesh Maniyam <[email protected]>
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Enable driver for Cadence NAND for the family
device agilex5. This driver is leveraged from the path
/drivers/mtd/nand/raw/cadence-nand-controller.c from the
stable version 6.11.2.
Signed-off-by: Dinesh Maniyam <[email protected]>
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If there is an unallocated memory area before the last, filling parting
the size calculation for MTD_SIZE_REMAINING does not take this hole
into account.
Fix this by calculating the remaining size just based on total size
and partition offset.
Signed-off-by: Alexander Stein <[email protected]>
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From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse time must be at least tREA.
Without this fix we got PMECC errors when reading, after switching to
ONFI timing mode 3 on SAM9X60 SoC with S34ML02G1 raw NAND flash chip.
The approach to set timings used before worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.
The approach to fix the issue was carried over from at91bootstrap, and
has been successfully tested in at91bootstrap, U-Boot and Linux.
Link: https://github.com/linux4sam/at91bootstrap/issues/174
Cc: Li Bin <[email protected]>
Signed-off-by: Alexander Dahl <[email protected]>
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Replace Maximumm with Maximum in Kconfig symbol description, fix a typo.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
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In the case of MTD_BLOCK and UBI_BLOCK they should be select'ing BLK as
they provide block device functionality and not depending on some other
block device already being enabled too (as is the typical case).
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Prepare v2025.01-rc6
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Update the spi_nor_read() function based on the config SPI_FLASH_BAR
and update the length and bank calculation by spliting the memory of
16MB size banks only when the address width is 3byte.
Fix the read issue for 4byte address width by passing the entire
length to the read function.
Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
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Prepare v2025.01-rc5
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This is a debug command to monitor the retention state of the data on
the array. The command needs a duplication of the mtd_read_oob()
function to actually return the maximum number of bitflips encountered
while reading the page. We could write a specific implementation for the
Sunxi driver but this is probably enough.
nand watch <off> <size> - check an area for bitflips
nand watch.part <part> - check a partition for bitflips
nand watch.chip - check the whole device for bitflips
The output may be a bit verbose and could look like:
=> nand watch.chip
device 0 whole chip
size adjusted to 0xff60000 (5 bad blocks)
NAND watch for bitflips in area 0x0-0xff60000:
Page 0 (0x00000000) -> error -74
Page 1 (0x00000800) -> error -74
Page 2 (0x00001000) -> error -74
Page 3 (0x00001800) -> error -74
Page 4 (0x00002000) -> error -74
Page 5 (0x00002800) -> error -74
Page 6 (0x00003000) -> error -74
Page 7 (0x00003800) -> error -74
Page 8 (0x00004000) -> error -74
Page 9 (0x00004800) -> error -74
Page 10 (0x00005000) -> error -74
Page 11 (0x00005800) -> error -74
Page 12 (0x00006000) -> error -74
Page 13 (0x00006800) -> error -74
Page 14 (0x00007000) -> error -74
Page 15 (0x00007800) -> error -74
Page 16 (0x00008000) -> error -74
Page 17 (0x00008800) -> error -74
Page 18 (0x00009000) -> error -74
Page 19 (0x00009800) -> error -74
Page 20 (0x0000a000) -> error -74
Page 21 (0x0000a800) -> error -74
Page 22 (0x0000b000) -> error -74
Page 23 (0x0000b800) -> error -74
Page 1110 (0x0022b000) -> up to 1 bf/chunk
Page 1122 (0x00231000) -> up to 1 bf/chunk
Page 1132 (0x00236000) -> up to 1 bf/chunk
Page 1362 (0x002a9000) -> up to 1 bf/chunk
Page 4990 (0x009bf000) -> up to 1 bf/chunk
Page 5728 (0x00b30000) -> up to 1 bf/chunk
Page 7116 (0x00de6000) -> up to 1 bf/chunk
Page 7160 (0x00dfc000) -> up to 1 bf/chunk
Page 7494 (0x00ea3000) -> up to 1 bf/chunk
Page 10842 (0x0152d000) -> up to 1 bf/chunk
Page 11614 (0x016af000) -> up to 1 bf/chunk
Page 11970 (0x01761000) -> up to 1 bf/chunk
Page 12536 (0x0187c000) -> up to 1 bf/chunk
Page 12687 (0x018c7800) -> up to 1 bf/chunk
Page 14298 (0x01bed000) -> up to 1 bf/chunk
Page 18268 (0x023ae000) -> up to 1 bf/chunk
Page 18760 (0x024a4000) -> up to 1 bf/chunk
Page 21440 (0x029e0000) -> up to 1 bf/chunk
Page 22336 (0x02ba0000) -> up to 1 bf/chunk
Page 22592 (0x02c20000) -> up to 1 bf/chunk
Page 23872 (0x02ea0000) -> up to 1 bf/chunk
Page 27584 (0x035e0000) -> up to 1 bf/chunk
Page 35008 (0x04460000) -> up to 1 bf/chunk
Page 37184 (0x048a0000) -> up to 1 bf/chunk
Page 41728 (0x05180000) -> up to 1 bf/chunk
Page 42176 (0x05260000) -> up to 1 bf/chunk
Page 43200 (0x05460000) -> up to 1 bf/chunk
Page 43328 (0x054a0000) -> up to 1 bf/chunk
Page 45376 (0x058a0000) -> up to 1 bf/chunk
Page 47040 (0x05be0000) -> up to 1 bf/chunk
Page 47552 (0x05ce0000) -> up to 1 bf/chunk
Page 49344 (0x06060000) -> up to 1 bf/chunk
Page 49856 (0x06160000) -> up to 1 bf/chunk
Page 62784 (0x07aa0000) -> up to 1 bf/chunk
Page 65153 (0x07f40800) -> up to 1 bf/chunk
Page 65228 (0x07f66000) -> up to 1 bf/chunk
Page 65382 (0x07fb3000) -> up to 1 bf/chunk
Page 98624 (0x0c0a0000) -> up to 1 bf/chunk
Page 101952 (0x0c720000) -> up to 1 bf/chunk
Page 107584 (0x0d220000) -> up to 1 bf/chunk
Page 118208 (0x0e6e0000) -> up to 1 bf/chunk
Page 126656 (0x0f760000) -> up to 1 bf/chunk
Page 127680 (0x0f960000) -> up to 1 bf/chunk
Page 129920 (0x0fdc0000) -> up to 1 bf/chunk
Maximum number of bitflips: 1
Pages with bitflips: 44/130752
It is also possible to reduce the output with the .quiet suffix in order
to just show the summary.
=> nand watch.chip
device 0 whole chip
size adjusted to 0xff60000 (5 bad blocks)
NAND watch for bitflips in area 0x0-0xff60000:
Maximum number of bitflips: 1
Pages with bitflips: 44/130752
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The condition 'ret' is always true as it is never set to other than
-EIO.
Remove 'ret' and the condition for copy.
Signed-off-by: Marcus Folkesson <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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Anurag Dutta <[email protected]> says:
Hi All,
In u-boot, hbmc is broken and has been removed from j7200
configs. This series re-enables the hbmc driver and introduces a series
of hyperflash boot fixes. At present, in u-boot, the parent device (fss)
gets registered as a syscon device. This is done because the MMIO
mux driver in u-boot did not support the mux functionality when the
parent device is not a syscon. In this series, we make relevant changes
in the hbmc driver as well as dts' so that we can use the reg-mux driver for
selecting the appropriate state of the mux.
Test logs:
1) j721e-idk-gw hyperflash boot test: https://gist.github.com/anuragdutta731/50aae6fec707a3ffad6d985de6757fe4
2) j7200-evm hyperflash boot test: https://gist.github.com/anuragdutta731/c3a4d60f8bfd9c425d6c44b36eb7322b
Link: https://lore.kernel.org/r/[email protected]
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The HBMC_AM654 driver was dependent on SYSCON because syscon APIs were
being used to select the multiplexer state. Change the dependency to
MULTIPLEXER and MUX_MMIO because mux APIs are now being used to
select mux state.
Signed-off-by: Anurag Dutta <[email protected]>
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The syscon APIs were used for selecting the state of the mux
device because the mmio-mux driver in u-boot did not support
the mux functionality when the parent device is not a syscon.
Change to mux APIs which utilizes the reg-mux driver to select the
state of the multiplexer.
Signed-off-by: Anurag Dutta <[email protected]>
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The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Prepare v2025.01-rc4
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Always probing pmecc in the generic nand controller probe function and
bailing out if pmecc is missing, prevents the driver to be usable for
SoCs which do not have a pmecc hardware ecc engine like older sam9 SoCs,
for example at91sam9g20. Tested on sam9x60 that the call, which the
comment was moved to, is sufficient to probe the pmecc.
Signed-off-by: Alexander Dahl <[email protected]>
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The bad CRC error message has transposed characters, which render the
output useless:
"bad CRC at record 213: #08x, not #08x" instead of
"bad CRC at record 213: #00000000, not #4be31f4d"
Fix the error message.
Signed-off-by: Benedikt Spranger <[email protected]>
Reviewed-by: John Ogness <[email protected]>
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Update log level messages so that more critical messages can be logged
to console and help the troubleshooting with field devices.
This is a port of the upstream Linux patch to U-Boot.
https://lore.kernel.org/linux-mtd/[email protected]/
Signed-off-by: david regan <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: William Zhang <[email protected]>
Reviewed-by: Anand Gore <[email protected]>
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Set parameter_page_big_endian to zero for bcmbca
Signed-off-by: david regan <[email protected]>
Reviewed-by: William Zhang <[email protected]>
Reviewed-by: Anand Gore <[email protected]>
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These device specific nand driver files can be removed because
they are now replaced by a common driver bcmbca_nand.c
Signed-off-by: david regan <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: William Zhang <[email protected]>
Reviewed-by: Anand Gore <[email protected]>
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While we want to compile the SPI_STACKED_PARALLEL code everywhere we
can, it must first be guarded with an #if for DM_SPI as not all cases
where we have this code built, such as in SPL, will have the relevant
DM_SPI option enabled.
Fixes: 43423cdc5dc1 ("mtd: spi-nor: Always build SPI_STACKED_PARALLEL code")
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Prevent the code gated by SPI_STACKED_PARALLEL from bitrot
by using if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) around
it. That way, it is always at least compiled.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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The SPI_ADVANCE description does not explain what the switch does.
It does not have anything to do with any advanced functionality, it
only gates off support for stacked and parallel SPI NORs. Rename the
Kconfig symbol, update description, and move it right next to Xilinx
hardware as it seems to be specific to this hardware. Make sure the
symbol is also protected by if DM_SPI in Kconfig.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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Rewrite the code to make it clear exactly where the
SNOR_F_HAS_PARALLEL flag leads to *2 and /2 operation
compared to regular code path. No functional change.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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The offset variable is set, but never used afterward.
Fix indent. Fix predecrement without justification.
Remove use of parenthesis where unnecessary.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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Remove undocumented SST special case. This was added in commit
5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
without any explanation in the commit message. Remove it.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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Remove undocumented write_disable() call. This was added in commit
5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
without any explanation in the commit message. Remove it.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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Remove undocumented set_4byte() call. This was added in commit
5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
without any explanation in the commit message. Remove it.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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Remove undocumented spi_nor_wait_till_ready() call. This was added in commit
5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
without any explanation in the commit message. Remove it.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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Remove undocumented nor->addr_width == 3 test. This was added in commit
5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
without any explanation in the commit message. Remove it.
This also has a bad side-effect which breaks READ operation of every SPI NOR
which does not use addr_width == 3, e.g. s25fs512s does not work at all. This
is because if addr_width != 3, rem_bank_len is always 0, and if rem_bank_len
is 0, then read_len is 0 and if read_len is 0, then the spi_nor_read() returns
-EIO.
Basic reproducer is as follows:
"
=> sf probe ; sf read 0x50000000 0 0x10000
SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Read: ERROR -5
"
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <[email protected]>
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Add SPI NOR flash id for mt35xu01gbba which supports 4 bytes address with
octal mode read.
Signed-off-by: Han Xu <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Added support for the Puya Semiconductor chips.
The datasheet can be found here:
https://www.puyasemi.com/h_xilie715.html
Signed-off-by: Dmitry Dunaev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The Infineon SEMPER NOR flash family uses 2-bit ECC by default with each
ECC block being 16 bytes. Under this scheme multi-pass programming to an
ECC block is not allowed. Set the writesize to make sure multi-pass
programming is not attempted on the flash.
Acked-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
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This patch follows the upstream linux commit:
5273cc6df984("mtd: spi-nor: core: Call spi_nor_post_sfdp_fixups() only
when SFDP is defined")
spi_nor_post_sfdp_fixups() was called regardless of if
spi_nor_parse_sfdp() had been called or not. late_init() should be
instead used to initialize the parameters that are not defined in SFDP.
Ideally spi_nor_post_sfdp_fixups() is called only after successful parse
of SFDP. However, in case SFDP support is disabled by .config, that can
break current functionality. Therefore, we would call it after
spi_nor_parse_sfdp() regardless of its return value.
Acked-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
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default_init() is wrong, it contributes to the maze of initializing
flash parameters. We'd like to get rid of it because the flash
parameters that it initializes are not really used at SFDP parsing time,
thus they can be initialized later.
Ideally we want SFDP to initialize all the flash parameters. If (when)
SFDP tables are wrong, we fix them with the post_sfdp/bfpt hooks, to
emphasize that SFDP is indeed wrong. When there are parameters that are
not covered by SFDP, we initialize them in late_init() - these
parameters have nothing to do with SFDP and they are not needed earlier.
With this we'll have a clearer view of who initializes what.
There are six default_init() hooks implemented just for initializing
octal_dtr_enable() and/or setup() hooks that called later on.
Just moving those to late_init() does not change functionality.
Suggested-by: Tudor Ambarus <[email protected]>
Acked-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
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The macronix_octal_fixups should be set only when mfr and flags match.
Fixes: df3d5f9e41 ("mtd: spi-nor: add support for Macronix Octal flash")
Acked-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
Cc: JaimeLiao <[email protected]>
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Some flashes like the Infineon SEMPER NOR flash family use ECC. Under
this ECC scheme, multi-pass writes to an ECC block is not allowed.
In other words, once data is programmed to an ECC block, it can't be
programmed again without erasing it first.
Upper layers like file systems need to be given this information so they
do not cause error conditions on the flash by attempting multi-pass
programming. This can be done by setting 'writesize' in 'struct
mtd_info'.
Set the default to 1 but allow flashes to modify it in fixup hooks. If
more flashes show up with this constraint in the future it might be
worth it to add it to 'struct flash_info', but for now increasing its
size is not worth it.
This patch replicates the following upstream linux commit:
afd473e85827 ("mtd: spi-nor: core: Allow flashes to specify MTD writesize")
Acked-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
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For NOR flashes EC and VID are zeroed out before an erase is issued to
make sure UBI does not mistakenly treat the PEB as used and associate it
with an LEB.
But on some flashes, like the Infineon Semper NOR flash family,
multi-pass page programming is not allowed on the default ECC scheme.
This means zeroing out these magic numbers will result in the flash
throwing a page programming error.
Do not zero out EC and VID for such flashes. A writesize > 1 is an
indication of an ECC-ed flash.
This patch replicates the following upstream linux commit:
f669e74be820 ("ubi: Do not zero out EC and VID on ECC-ed NOR flashes")
Acked-by: Tudor Ambarus <[email protected]>
Acked-by: Pratyush Yadav <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
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The Broadcom BCA platforms are broadband access SoCs.
This is a port of the upstream Linux driver to U-Boot.
It was based on drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
from Linux v6.11.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
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When ECC parameters are not specified in DT, first try ONFI ECC parameters
before fallback to maximum strength.
It's the Linux driver behavior since the driver rewriting in f88fc12.
From then 2 nand system refactors have been done in 6a1b66d6 and 53576c7b,
chip->ecc_strength_ds and chip->ecc_step_ds became
nanddev_get_ecc_requirements(). U-Boot didn't follow the refactor and
always use these 2 fields.
v2: Fix formatting, add upstream commit hash.
Signed-off-by: Zixun LI <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Acked-by: Balamanikandan Gunasundar
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Simon Glass <[email protected]> says:
When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL
Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.
For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.
This series starts a change in terminology and usage to resolve the
above issues:
- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_
It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.
This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.
The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
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Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.
Update the comment in bootstage to refer to this symbol, instead of
SPL_
Signed-off-by: Simon Glass <[email protected]>
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Use the new symbol to refer to any 'SPL' build, including TPL and VPL
Signed-off-by: Simon Glass <[email protected]>
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Give this function a slightly easier name.
Signed-off-by: Simon Glass <[email protected]>
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Infineon S28HS256T is 256Mb Octal SPI device which has same
functionalities with 512Mb and 1Gb parts.
Link:https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
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S28HS02GT is dual-die package parts and do not support chip erase.
Fixes: 16dd1095101 ("mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID")
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
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S25HL02GT and S25HS02GT are dual-die package parts and do not support
chip erase.
Fixes: c95a914aed7 ("mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t")
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: Takahiro Kuwano <[email protected]>
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