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Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for Spansion S25FL512S_64K SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q1024A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q1024 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q512A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q512 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)
With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.
As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for Winbond W25QXXXFV SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Winbond W25Q16DW SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Winbond W25Q128FW SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Use the exact names for W25Q 0x40XX ID's flash parts, as the same
sizes of flashes comes with different ID's. so-that the distinguishes
becomes easy with this change.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Corrected the name of S25FL128S 64K sector part SPI flash,
S25FL128S supported has been added in below commit
"sf: spansion: Add support for S25FL128S"
(sha1: 1bfb9f156aa66cca6bb9c773867a1f02a84b14be)
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds
common/Makefile: Avoid compiling unnecssary files
fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Conflicts:
spl/Makefile
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commit dfe64e2c89731a3f9950d7acd8681b68df2bae03
Author: Sergey Lapin <[email protected]>
Date: Mon Jan 14 03:46:50 2013 +0000
mtd: resync with Linux-3.7.1
changed the initialization of BBT options. Fix drivers
jz4740 and s3c2410 which have not been updated yet and
cause compile errors.
Signed-off-by: Daniel Schwierzeck <[email protected]>
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Commit dfe64e2c89731a3f9950d7acd8681b68df2bae03:
mtd: resync with Linux-3.7.1
broke the docg4 driver. Specifically:
- some of the prototypes of the ecc methods changed
- the NAND_NO_AUTOINCR flag was removed
- the ecc.strength element was added.
This patch fixes these. Tested on the docg4 on my palmtre680 board.
Signed-off-by: Mike Dunn <[email protected]>
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This patch corrected the nr_blocks used for W25Q32DW SPI flash.
nr_blcoks are incorrectly assigned on below patch
"sf: winbond: add W25Q32DW"
(sha1: 772ba15474f73adc942e817cc072b6e9750836cc)
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Winbond W25Q80BW SPI flash.
This patch corrected the flash name, nr_blocks and
also commit message header from below patch.
"sf: winbond: add W25Q32"
(sha1: c969abc47033d6f810d3c9dbdb994ea9d691d038)
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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As the per the ID tabl the flash is under Uniform 64-kB sector
architecture, hence updated with proper name.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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commit dfe64e2c89731a3f9950d7acd8681b68df2bae03
Author: Sergey Lapin <[email protected]>
Date: Mon Jan 14 03:46:50 2013 +0000
mtd: resync with Linux-3.7.1
Introduced runtime bug:
U-Boot 2013.04-00499-g46567df-dirty (Jun 04 2013 - 08:17:08)
I2C: ready
DRAM: 512 MiB
WARNING: Caches not enabled
NAND: BUG: failure at nand_base.c:3214/nand_scan_tail()!
BUG!
resetting ...
on boards using drivers/mtd/nand/omap_gpmc.c as in board_nand_init()
nand->ecc.strength is not set. Fix this!
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Sergey Lapin <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Tom Rini <[email protected]>
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This patch adds a print messages while using 'sf read' and
'sf write' commands to make sure that how many bytes read/written
from/into flash device.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Acked-by: Tom Rini <[email protected]>
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This patch adds a print messages while using 'sf erase' command
to make sure that how many bytes erased in flash device.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Acked-by: Tom Rini <[email protected]>
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Missing return after memcpy is done for memory-mapped SPI flashes,
hence added retun 0 after memcpy done.
The return is missing in below patch
"sf: Enable FDT-based configuration and memory mapping"
(sha1: bb8215f437a7c948eec82a6abe754c226978bd6d)
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:
- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.
- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).
To produce this update I used tag v3.7.1 of linux-stable repository.
The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.
Signed-off-by: Sergey Lapin <[email protected]>
[[email protected]: some eccstrength and build fixes]
Signed-off-by: Scott Wood <[email protected]>
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Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
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Add support for Winbond's W25PXX SPI flash.
These devices is used on Faraday A369 evaluation board.
Signed-off-by: Kuo-Jung Su <[email protected]>
CC: Jagannadha Sutradharudu Teki <[email protected]>
CC: Tom Rini <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Winbond W25Q256 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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This is a S25FL064A successor. It supports up to 104MHz bus
speed.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Mike Frysinger <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.
Signed-off-by: Xie Xiaobo <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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When base address given was out of valid flash address ranges,
flash_get_info() function returned the pointer to the last
element of flash_info[i] array.
This patch changes this function to return NULL pointer
in such a case, which is more correct behaviour.
The function flash_protect_default() calls flash_protect()
immediately after flash_get_info() invocation.
With this correction, flash_protect() function would be
able to return soon, for NULL flash_info.
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Linux Kernel Documentation/CodingStyle says:
Do not add a space after unary operators such as &, *, ...
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Packed structure cfi_qry contains unaligned 16- and 32-bits members,
accessing which causes problems when cfi_flash driver is compiled with
-munaligned-access option: flash initialization hangs, probably
due to data error.
Since the structure is supposed to replicate the actual data layout
in CFI Flash chips, the alignment issue can't be fixed in the structure.
So, unaligned fields need using of explicit unaligned access macros.
Signed-off-by: Andrew Gabbasov <[email protected]>
Reviewed-By: Albert ARIBAUD <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Convert NAND IFC driver to support CONFIG_SYS_NAND_SELF_INIT.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
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When a all 0xFF buffer is passed to drop_ffs, the no-0xFF check loop
will loop forever.
After the fix, If ssize_t i = -1 and size_t l = i + 1, the value of l
will still be 0 as expected.
Signed-off-by: Tao Hou <[email protected]>
Cc: Ben Gardiner <[email protected]>
Cc: Scott Wood <[email protected]>
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When writelen is mtd->writesize - 1, it is still a partial page write
Signed-off-by: Tao Hou <[email protected]>
Cc: Scott Wood <[email protected]>
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This avoids needing a separate U-Boot config when some revisions
of a board have small-page NAND and other revisions have large-page
NAND (except for NAND SPL targets).
CONFIG_FSL_ELBC_FMR is removed -- it was never used nor documented, and
it gets in the way of this change.
Signed-off-by: Scott Wood <[email protected]>
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This patch adds driver for the gigabyte devices
GD25LQ and GD25Q64B required for Snow Board.
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The manual resolution in commit ec7023db wrongly removed functions
nand_init and nand_deselect from file drivers/mtd/nand/mxc_nand_spl.c.
Revert this removal.
Signed-off-by: Albert ARIBAUD <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Conflicts:
drivers/mtd/nand/mxc_nand_spl.c
include/configs/m28evk.h
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This patch adds a driver for the diskonchip G4 nand flash device. It is based
on the driver from the linux kernel.
This also includes a separate SPL driver. A separate SPL driver is used because
the device operates in a different mode (reliable mode) when loading a boot
image, and also because the storage format of the boot image is different from
normal data (pages are stored redundantly). The SPL driver basically mimics how
a typical IPL reads data from the device. The special operating mode and
storage format are used to compensate for the fact that the IPL does not contain
the BCH ecc decoding algorithm (due to size constraints). Although the u-boot
SPL *could* use ecc, it operates like an IPL for the sake of simplicity and
uniformity, since the IPL and SPL share the task of loading the u-boot image.
As a side benefit, the SPL driver is very small.
[port from linux kernel 3.4 commit 570469f3bde7f71cc1ece07a18d54a05b6a8775d]
Signed-off-by: Mike Dunn <[email protected]>
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