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Add support for Numonyx N25Q256A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add support for Numonyx N25Q32A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add support for Numonyx N25Q32 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add support for Numonyx N25Q64A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add support for Winbond's W25Q64W SPI flash.
This device is used on xilinx zynq emulation platform.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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This patch corrected the first byte of idcode1 for S25FL256S SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add support for Numonyx N25Q064 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Report the usage of the Advanced Sector Protection (PPB) to the user
upon 'flinfo' command. E.g:
Bank # 1: CFI conformant flash (16 x 16) Size: 64 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2301
Advanced Sector Protection (PPB) enabled
Erase timeout: 16384 ms, write timeout: 2 ms
Buffer write timeout: 5 ms, buffer size: 32 bytes
Sector Start Addresses:
FC000000 E FC020000 E RO FC040000 E FC060000 E FC080000 E
...
Signed-off-by: Stefan Roese <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Holger Brunck <[email protected]>
Tested-by: Holger Brunck <[email protected]>
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Not only Spansion supports the Persistent Protection Bits (PPB) locking.
Other devices like the Micron JS28F512M29EWx also support this type
of locking/unlocking. Detection of support is done in the same way as
done for the Spansion chips - via the 0x49 CFI word.
This patch enables this PPB protection mechanism for all AMD type
(AMD commandset) chips.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Holger Brunck <[email protected]>
Tested-by: Holger Brunck <[email protected]>
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Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector
protection] introduced the PPB (Persistent Protection Bit) locking for
Spansion chips. But right now the sector protection status (locked vs
unlocked) is set to unlocked for all sectors upon bootup. The real
sector protection status is ignored.
This patch now reads the current sector protection status and uses
it for these AMD/Spansion flash chips.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Holger Brunck <[email protected]>
Tested-by: Holger Brunck <[email protected]>
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Consolidate manufacturer matching into the function manufact_match()
and use it.
Signed-off-by: Stefan Roese <[email protected]>
Tested-by: Holger Brunck <[email protected]>
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Add support for SST 4KB sector granularity.
Many recent SST flashes, i.e. SST39VF3201B and similar of this family
are declared CFI-conformant from SST. They support CFI query, but implement
2 different sector sizes in the same memory: a 64KB sector (they call it
"block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector",
erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh
of cfi query struct, detects a number of secotrs for the 4KB granularity
(flinfo shows it).
For all other aspects, they are CFI compliant, so, as Linux do, i think
it's a good idea to handle these chips in the CFI driver, with a fixup
to allow 4KB granularity, as should be expected, instead of 64KB.
Signed-off-by: Angelo Dureghello <[email protected]>
Signed-off-by: Stefan Rose <[email protected]>
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Signed-off-by: Albert ARIBAUD <[email protected]>
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This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
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IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.
NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Hemant Nautiyal <[email protected]>
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It could happen (1 out of 100 times) that NAND did not start up correctly after
warm rebooting, so we end up with various failures or DMA timed out due to a
stalled BCH. When resetting BCH together with GPMI, the issue could not be
observed anymore (after 10000+ reboots). We probably need the consistent state
already before sending commands to NAND. This behaviour was observed in barebox
and kernel, so I assume it affects U-Boot as well. I chose to keep the extra
reset for BCH when changing the flash layout to be on the safe side.
Signed-off-by: Wolfram Sang <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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AM33XX with BCH8 can't work with nand_spl_simple correctly
because custom read_page implementation is required for proper
syndrome generation.
This simple driver mostly duplicates nand_spl_simple but has
nand_read_page changed to suit our needs.
Signed-off-by: Ilya Yanok <[email protected]>
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This patch adds support for BCH8 error correction code to omap_gpmc
driver. We use GPMC to generate codes/syndromes but we need ELM to find
error locations from given syndrome.
Signed-off-by: Mansoor Ahamed <[email protected]>
[ilya: merge it with omap_gpmc driver, some fixes and cleanup]
Signed-off-by: Ilya Yanok <[email protected]>
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This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.
This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
[[email protected]: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <[email protected]>
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NAND Flash is erased by blocks, not by pages.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
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This patch cleans up nand_util.c:
- Fix tabs.
- Fix typos.
- Remove space character before opening parenthesis in function calls.
- Fix comments.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
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Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).
This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: Joe Hershberger <[email protected]>
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IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.
Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[[email protected]: fix fsl_ifc_sram_init prototype]
Signed-off-by: Scott Wood <[email protected]>
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These controllers can only do hardware ECC on full page transfers.
Signed-off-by: Scott Wood <[email protected]>
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Document parameters used for specifying the NAND image to be loaded.
Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory. The word "simple" is
there for a reason. :-)
Signed-off-by: Scott Wood <[email protected]>
---
v2: updated for makefile changes earlier in patchset
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Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <[email protected]>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
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nand_ecc.c:82:5: warning: symbol 'nand_calculate_ecc' was not declared. Should it be static?
nand_ecc.c:155:5: warning: symbol 'nand_correct_data' was not declared. Should it be static?
nand_base.c:2854:1: error: directive in argument list
nand_base.c:2856:1: error: directive in argument list
Signed-off-by: Kim Phillips <[email protected]>
Acked-by: Scott Wood <[email protected]>
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cfi_flash.c:756:43: warning: Using plain integer as NULL pointer
cfi_flash.c:1150:52: warning: cast to non-scalar
cfi_flash.c:1433:46: warning: cast truncates bits from constant value (890089 becomes 89)
cfi_flash.c:1490:61: warning: cast truncates bits from constant value (1f001f becomes 1f)
cfi_flash.c:1508:61: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1738:63: warning: cast truncates bits from constant value (10001 becomes 1)
cfi_flash.c:1857:6: warning: symbol '__flash_cmd_reset' was not declared. Should it be static?
Signed-off-by: Kim Phillips <[email protected]>
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u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <[email protected]>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <[email protected]>
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Add the missing bits to the Tegra NAND driver to make ONFI detection work
properly.
Also add it to the Tegra default config, as it seems to be a reasonable thing
to have it available on all boards that use any kind of NAND.
Signed-off-by: Lucas Stach <[email protected]>
Acked-by: Scott Wood <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Boards may require a different pinmux setup for NAND than the default one.
Add a way to call into board specific code to set this up.
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.
All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.
Signed-off-by: Tom Warren <[email protected]>
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Due to grown code sizes the TQM85xx boards don't build any more with
some older tool chains (like ELDK 4.2). As these boards have long
reached EOL it seems a waste of effort trying to fix them. The vendor
has agreed to drop support for them, too. So let's get rid of them.
Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Stefan Roese <[email protected]>
cc: Kim Phillips <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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In board_nand_init() we only need the 'tmp' variable if MXC_NFC_V2_1 is
defined.
Signed-off-by: Tom Rini <[email protected]>
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Use the same IP revisions as in Linux in order to make the comparison more
clear.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Merge mxc_setup_config1() into board_nand_init() in order to ease the addition
of i.MX5 support in the following patches.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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mxc_nand_read_page_raw_syndrome() should reenable ECC upon exit. This fixes ECC
errors left uncorrected after a call to this function.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Use _mxc_nand_enable_hwecc() instead of duplicating its code.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2
consecutive 16-bit registers. This patch reads all the fields of this value,
which makes a difference for 4-kiB NF pages.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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This patches fixes the TODO to use same register definitions in mtd mxc_nand and
nand_spl fsl nfc drivers.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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This is based on Linux kernel -next:
commit 14f44abf1dafc20ba42ce8616a8fc8fbd1b3712b
Author: Brian Norris <[email protected]>
Date: Fri Jul 13 09:28:24 2012 -0700
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Brian Norris <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Scott Wood <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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NAND_CMD_ constants for lock/unlock should be in the header
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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