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Missed in previous cleanup.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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NAND unlock command allows an invert bit to be set to unlock all but
the selected page range.
Signed-off-by: Joe Hershberger <[email protected]>
[[email protected]: updated docs and added comment about invert bit]
Signed-off-by: Scott Wood <[email protected]>
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With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Artem: split long line on 2 shorter ones.
This is commit 637957551c0ac80de8dfc7650d320c5a98c2c0c0 from Linux
Signed-off-by: Matthieu Castet <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
[[email protected]: picked from Linux into U-Boot]
Reported-by: Rafael Beims <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Using common spi flash operation function to replace private operation
funtion
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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Add atmel at25df321 serial flash support
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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enable.
Before the patch, it looks like:
|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:11:06)
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|CPU: AT91SAM9G35
|Crystal frequency: 12 MHz
|CPU clock : 400 MHz
|Master clock : 133.333 MHz
|DRAM: 128 MiB
|WARNING: Caches not enabled
> |NAND: Initialize PMECC params, cap: 2, sector: 512
> |256 MiB
|MMC: mci: 0
|In: serial
|Out: serial
|Err: serial
|Net: macb0
|Hit any key to stop autoboot: 0
After the patch:
|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:18:11)
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|CPU: AT91SAM9G35
|Crystal frequency: 12 MHz
|CPU clock : 400 MHz
|Master clock : 133.333 MHz
|DRAM: 128 MiB
|WARNING: Caches not enabled
> |NAND: 256 MiB
| ... ...
|Hit any key to stop autoboot: 0
Signed-off-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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With Simon Glass's include/nand.h alignment changes, some mxs builds
were generating errors. Fix is to ensure asm/cache.h is included before
linux/mtd/nand.h. Moving common.h to top of include list does that.
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Scott Wood <[email protected]>
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Check for ctrlc() in operations that take time and loop over the flash
addresses.
In netconsole, tstc() is expensive. Only check once in a while to not
slow down the operation significantly.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Added an optional check in the CFI driver to evaluate if the sector is
already blank before issuing an erase command. Improves erase time by
over a factor of 10 if already blank.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The Programmable Multibit ECC (PMECC) controller is a programmable binary
BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
can be used to support both SLC and MLC NAND Flash devices. It supports to
generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.
To use PMECC in this driver, the user needs to set the PMECC correction
capability, the sector size and ROM lookup table offsets in board config file.
This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference
is in this version it uses registers structure access hardware instead of using macros.
It is tested in 9x5 serial boards.
Signed-off-by: Josh Wu <[email protected]>
[rebase]
Signed-off-by: Andreas Bießmann <[email protected]>
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Signed-off-by: Josh Wu <[email protected]>
Acked-by: Scott Wood <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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atmel_hw_nand_init_param().
This patch
1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support.
2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail().
Signed-off-by: Josh Wu <[email protected]>
[fix empty newline at EOF error and move return value check into ifdef]
Signed-off-by: Andreas Bießmann <[email protected]>
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The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.
Signed-off-by: Otavio Salvador <[email protected]>
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Orjan Friberg wrote at [1]:
"For the beagleboard, ecc.size is not explicitly set when doing 'nandecc
sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's
set to 256 bytes.
When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when
changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly
the format has changed."
No patch has been submitted and the issue was still present. This patch
adds the mentioned solution. Tested on a tam3517 board.
[1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html
cc: Orjan Friberg <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
Acked-by: Nikita Kiryanov <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
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Signed-off-by: Otavio Salvador <[email protected]>
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* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: Add support for S25FL256S
sf: winbond: fix page_size
sf: stmicro: add support for N25Q128A
sf: stmicro: add support N25Q128 parts
sf: stmicro: support JEDEC standard two-byte signature
sf: winbond: add W25Q32
cmd_spi: remove superfluous semicolon
Signed-off-by: Wolfgang Denk <[email protected]>
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Add support for Spansion S25FL256S SPI flash.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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Commit a4ed3b6 "sf: inline data constants" modified winbond.c's page_size
from 256 to 4096. This prevents either/both of "sf write" writing the
correct data, or "sf read" from reading the correct data back.
This allows U-Boot running on Compulab Tegra to upgrade itself.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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commit 54652991
Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips
fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads
to problems for smaller versions of this chip e.g. the 32Mbit version
with deviceid 0x16 on mgcoge. So move the code for this work around to
an own function and check previously manufacturer id and device id to
not break other flashes which don't need this work around.
Signed-off-by: Holger Brunck <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
cc: Stefan Roese <[email protected]>
cc: Philippe De Muyter <[email protected]>
cc: Gerlando Falauto <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Erasing flash sectors protected with persistent protection bit (PPB)
mechanism on Spansion flash chips doesn't work. Add sector protection
status checking and sector lock and unlock commands to fix this.
Signed-off-by: Anatolij Gustschin <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Add support for Numonyx N25Q128A SPI flash.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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Adds support for Numonyx's N25Q128 SPI flash. These devices
are used on (among others) Avnet Spartan-6 LX9 micro-evaluation
boards. Tested with "sf" commands and CONFIG_ENV_IS_IN_SPI_FLASH.
Signed-off-by: Stephan Linz <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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There are more than the M25Pxx serial flashs that can be
used with the stmicro driver, for example: the M25PXxx or
N25Qxx serie. All these chips have burned in the original
stmicro manufacture id 0x20 together with a standard
two-byte signature.
In preperation to support all these chips the stmicro driver
have to decode the full two-byte signature.
Signed-off-by: Stephan Linz <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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SMDK EVT1 has a different Winbond part, added its part details
to the SPI flash table.
Signed-off-by: Abhilash Kesavan <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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Note: because 4-byte addressing is not supported yet,
at the moment only the first 16MiB of the device are available.
Signed-off-by: Jérôme Carretero <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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The only two drivers to write the status register do it in the same
way, so unify the implementations. This also makes the block unlock
logic the same.
Signed-off-by: Mike Frysinger <[email protected]>
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The local sst enable/disable write funcs don't really add anything
over the common API, so just inline the common calls directly.
Signed-off-by: Mike Frysinger <[email protected]>
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Looks like Shaohui Xie's patch got merged twice.
Signed-off-by: Mike Frysinger <[email protected]>
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Analysis of the flash drivers shows that they all use 0x20 if the erase
size is 4KiB, or 0xd8 if it's larger. So with this info in hand, we can
unify all the erase functionality in one place.
Signed-off-by: Mike Frysinger <[email protected]>
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I imagine much of these constants are due to copy & pasting previous
drivers rather than an actual reflection of the hardware layout. At
any rate, inline the info that we don't care about externally as it
shrinks things nicely.
Signed-off-by: Mike Frysinger <[email protected]>
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No need for dedicated defines when these really only get used once.
Signed-off-by: Mike Frysinger <[email protected]>
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In an effort to unify the spi flash drivers further, drop all the
unused and/or duplicate command defines.
Signed-off-by: Mike Frysinger <[email protected]>
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Needed for redundant environment for example.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Amit Virdi <[email protected]>
Cc: Vipin Kumar <[email protected]>
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Signed-off-by: Armando Visconti <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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There are two problems in the current timeout loop implementation:
1. In case initial test failing, there will always be a delay of 1 ms
2. The delay duration is not tunable
The new implementation addresses both these limitations.
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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If the flash size was smaller than 1MB then flash_print_info()
was erroneously reporting 0 MB.
Signed-off-by: Armando Visconti <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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THis patch introduces a new methodology for flash probing
in which flash_devices[] table, looked-up thru the dev_id, is
used to locate the flash geometry and information.
Signed-off-by: Armando Visconti <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Since the smi erase code is very generic and works for any kind
of flash, there is no need to test for ST_M25Pxx_ID flash types
like m25p40 flashes).
Signed-off-by: Armando Visconti <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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smi_read_sr fails sometimes because of TFF not getting set within assumed time.
This condition may arise because of, for example, smi memory being in a erase
mode.
This fix is to enable reading the status register until timeout.
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Shiraz Hashim <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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SMI driver read status fails because the control register could not be
overwritten. Instead, the read status should be tried until timeout.
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This commit does the following:
- Reports error if SNOR flash is not found on the board
- Changes smi_read_sr to return error using which a retry mechanism is
implemented for reading flash status
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Curently the code makes wrong assumption that the Transfer finished flag shall
be set within the stipulated time. However, there may occur a scenario in which
the TFF flag is not set. Return error in that case.
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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SMI is the serial memory interface controller provided by ST.
Earlier, a driver exists in the u-boot source code for the SMI IP. However, it
was specific to spear platforms. This commit converts the same driver to a more
generic driver. As a result, the driver files are renamed to st_smi.c and
st_smi.h and moved into drivers/mtd folder for reusability by other platforms
using smi controller peripheral.
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Since, SPEAr platform uses generic FSMC driver now, so spear specific files
drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are
removed
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Scott Wood <[email protected]>
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Flexible static memory controller is a peripheral provided by ST,
which controls the access to NAND chips along with many other
memory device chips eg NOR, SRAM.
This patch adds the driver support for FSMC controller interfacing
with NAND memory.
Signed-off-by: Vipin Kumar <[email protected]>
Signed-off-by: Amit Virdi <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Scott Wood <[email protected]>
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This chip is present on the Compulab TrimSlice.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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* 'master' of git://git.denx.de/u-boot-nand-flash:
NAND: Remove ONFI detection message to from bootup log
driver/mtd:IFC: Fix possible memory leak
driver/mtd: IFC NAND: Add support of ONFI NAND flash
mtd, nand: move some printfs to debug output.
nand_util: correct YAFFS image write function
powerpc/85xx: fix NAND boot linker scripts for -fpic
nand: extend .raw accesses to work on multiple pages
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