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USER_DATA register offset moved in H616, so let's make it a SoC cap
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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ECC_ERR_CNT register offset moved in H616, so let's make it a SoC cap
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Introduce per SoC capabilities in sunxi_nand.c
This prepares for the H616 support that has quite a lot differences in
registers offset and capabilities.
Start with the ECC strength table.
No functional change.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Merge common register definitions from sunxi_nand{,_spl}.c
The Allwinner NAND controller registers where in both files, so let's
just merge all that in a header, it will be easier for maintenance.
NB: the defines are also harmonized with Linux driver
No functional change
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The sunxi_ccm_reg is legacy, drop its usage from nand related code
For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock
files when missing.
And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the
new scheme.
Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N
Suggested-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Remove unneeded definitions NFC_CMD_R* in sunxi_nand_spl.c
No need to define NFC_CMD_RNDOUTSTART, NFC_CMD_RNDOUT and
NFC_CMD_READSTART here since they are already in linux/mtd/rawnand.h
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Harmonize registers definition in sunxi_nand{,_spl}.c files
This is a first step to then include the same file from both
sunxi_nand{,_spl}.c files
Unused defines are also removed
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Fix pointer from interget warning when compiling for ARM64
When compiling for arm64, we get this error:
error: passing argument 2 of ‘__memcpy_fromio’ makes pointer from
integer without a cast [-Wint-conversion]
Moreover the copy should be made with dedicated readl(), like for any
register access on this peripheral, since they are 32bit wide.
So, instead of memcpy_fromio(), just use a readl() loop.
Introduce nand_readlcpy() to implement this loop.
Fixes: 6ddbb1e936c7 ("spl: nand: sunxi: use PIO instead of DMA")
Suggested-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Remove 'complete' member from struct sunxi_nfc
The 'complete' member isn't part of the structure, let's remove it.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Prepare v2026.01-rc4
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The ALTERA_QSPI driver conflicts with the regular FLASH_CFI_DRIVER as
both implement the same high level functionality and so use the same
global namespace. In a similar fashion, all NAND drivers are mutually
exclusive due to namespace collisions. For the remaining drivers which
did not already have some architecture specific dependency, add them.
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2026.01 cycle:
This small fixes set includes a fix on the mtd pmecc driver.
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Enable ONFI parameter page detection for SoCFPGA SoC64 devices by
selecting SYS_NAND_ONFI_DETECTION in the NAND_DENALI Kconfig entry.
This allows SoCFPGA SoC64 platforms using the Denali NAND controller
to automatically detect NAND parameters via the ONFI interface instead
of relying on hardcoded configuration values.
The selection is limited to TARGET_SOCFPGA_SOC64 to avoid affecting
non-SoC64 platforms that use legacy NAND handling.
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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"timing" and "timing_res_idx" are unused and not exist in Linux driver,
let's remove them.
Signed-off-by: Zixun LI <[email protected]>
Acked-by: Alexander Dahl <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
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Setup the pmecc data setup time as 3 clock cycles for 133MHz as
recommended by the datasheet.
Backported from Linux: f55f552a7c7e0a1 ("mtd: rawnand: atmel: set pmecc
data setup time")
Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver")
Signed-off-by: Zixun LI <[email protected]>
Tested-by: Alexander Dahl <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
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This option is only meaningful within the davinci nand driver, so drop
the statement here (which had no effect).
Signed-off-by: Tom Rini <[email protected]>
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Add support for FudanMicro FM25S01A SPI NAND.
This driver is ported from linux v6.18 and tested on a MT7981 board.
Link: https://lore.kernel.org/linux-mtd/[email protected]/
Reviewed-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
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The hidden symbol SPL_SYS_NAND_SELF_INIT was not being used correctly
leading to Kconfig dependency issues seen with "make allyesconfig". As
it's a select'd symbol we don't need to have a depends line on it, and
then in turn we need to also update the logic on SYS_NAND_PAGE_SIZE and
SYS_NAND_OOBSIZE.
Signed-off-by: Tom Rini <[email protected]>
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All these chips are dual and quad capable. They are also DTR capable,
but the core is not yet ready for that.
Performances of all chips are comparable at 30MHz and are as follow:
Eraseblock single read speed: 938kiB/s
Eraseblock dual read speed: 1068kiB/s
Eraseblock quad read speed: 3751kiB/s
Signed-off-by: Miquel Raynal <[email protected]>
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When printing the contents of an lbaint_t variable we need to use LBAF
to print it in order to get the correct format type depending on 32 or
64bit-ness.
Signed-off-by: Tom Rini <[email protected]>
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When printing the contents of an size_t variable we need to use z prefix
to the format character in order to get the correct format type
depending on 32 or 64bit-ness.
Signed-off-by: Tom Rini <[email protected]>
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This feature requires that CFG_SYS_FLASH_BASE is defined and this in
turn is only done in the case of FLASH_CFI_DRIVER && !CFI_FLASH or in
other words, when DM_MTD is not enabled.
Signed-off-by: Tom Rini <[email protected]>
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In nand_wait_ready there is a loop that includes a NULL check for
chip->dev_ready before it is dereferenced. Use a NULL check once the
loop is exited as well to cover the case where it exits due to a timeout
and it is therefore not known if chip->dev_ready is NULL or not.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-nand-flash
This series adds significant and valuable work by Mikhail Kshevetskiy to
align spi-mem with Linux 6.16. It also includes contributions to the mtd
performance patches, a work started by Miquel Raynal and improved by
Mikhail Kshevetskiy. Additionally, two patches tighten dependencies on
the Atmel driver.
The patches pass the pipeline CI:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/27873
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The way that the NAND driver under DM_NAND_ATMEL is probed is by the
dummy memory driver controlled by ATMEL_EBI. Rather than require that
for NAND to work both be enabled, make NAND select ATMEL_EBI and do not
prompt for ATMEL_EBI as it only triggers the probe for NAND.
Signed-off-by: Tom Rini <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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A large number of mtd drivers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.
Signed-off-by: Tom Rini <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-ubi
UBI updates for 2025.10
- ubi fixes found by Andrew with Smatch
- mtd: ubi: Remove test that always fails
- fs: ubifs: Ensure buf is freed before return
- fs: ubifs: Need to check return for being an error pointer
-fs: ubifs: Fix and rework error handling in ubifs_finddir
- fix: limit copy size in ubispl found by Benedikt
- extend support for LED activity (use the LED activity also on ubi reads)
from Yegor
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We have a large number of library symbols that should not be prompted
for by the user really but rather selected by the platform (or SoC) as
needed. To start with however, make these depend on !COMPILE_TEST.
Signed-off-by: Tom Rini <[email protected]>
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The fastmap VID header is embedded in struct ubi_scan_info. During fastmap
scan, the header is copied into struct ubi_scan_info, if valid. The former
code mixed up the amount of copied bytes and copied more bytes than
nessesary. This had no side effect, since the affected struct members are
uninitialized at that point and overwritten later.
Limit the copied bytes to the VID header size.
Signed-off-by: Benedikt Spranger <[email protected]>
Reported-by: Andrew Goodbody <[email protected]>
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When checking the VID header of a static volume there is an early test
for data_size == 0 so testing for that condition again is guaranteed to
fail. Just remove this piece of code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Continuous reading may result in multiple flash pages reading in one
operation. Unfortunately, not all spinand controllers support such
large reading. They will read less data. Unfortunately, the operation
can't be continued.
In this case:
* disable continuous reading on this (not good enough) spi controller
* repeat reading in regular mode.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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reading fails
Continuous reading may result in multiple flash pages reading in one
operation. Typically only one flash page has read/written (a little bit
more than 2-4 Kb), but continuous reading requires the spi controller
to read up to 512 Kb in one operation without toggling CS in beetween.
Roughly speaking spi controllers can be divided on 2 categories:
* spi controllers without dirmap acceleration support
* spi controllers with dirmap acceleration support
Firt of them will have issues with continuous reading if restriction on
the transfer length is implemented in the adjust_op_size() handler.
Second group often supports acceleration of single page only reading.
Thus enabling of continuous reading can break flash reading.
This patch tries to create dirmap for continuous reading first and
fallback to regular reading if spi controller refuses to create it.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Continuous mode is only supported for data reads, thus writing
requires only single flash page mapping.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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This makes the U-Boot SPI NAND driver almost the same as in Linux
6.17-rc1. The only major differences are:
* support of ECC engines. The Linux driver supports different ECC
engines while U-Boot uses on-die ECC only.
* per operation maximum SPI bus frequency
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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There is already a manufacturer hook, which is manufacturer specific but
not chip specific. We no longer have access to the actual NAND identity
at this stage so let's add a per-chip configuration hook to align the
chip configuration (if any) with the core's setting.
This is a port of linux commit
da55809ebb45 ("mtd: spinand: Add a ->configure_chip() hook")
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Since commit 3d1f08b032dc ("mtd: spinand: Use the external ECC engine
logic") the spinand_write_page() function ignores the errors returned
by spinand_wait(). Change the code to propagate those up to the stack
as it was done before the offending change.
This is a port of linux commit
091d9e35b85b ("mtd: spinand: propagate spinand_wait() errors from spinand_write_page()")
Signed-off-by: Gabor Juhos <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Signed-off-by: Michael Trimarchi <[email protected]>
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Currently the best variant picked in the first one in the list provided
in the manufacturer driver. This worked well while all operations where
performed at the same speed, but with the introduction of DTR transfers
this no longer works correctly.
Let's continue iterating over all the alternatives, even if we find a
match, keeping a reference over the theoretically fastest
operation. Only at the end we can tell which variant is the best.
This logic happening only once at boot.
The patch is based on linux commit
666c299be696 (mtd: spinand: Enhance the logic when picking a variant)
created by Miquel Raynal <[email protected]>
The code was a bit restricted in the functionality since not all
required functionality is supported in the u-boot.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The code was ported from linux-6.15
based on a linux commit c06b1f753bea (mtd: spinand: add OTP support)
created by Martin Kurbanov <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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When the host ECC fails to correct the data error of NAND device,
there's a special read for data recovery method which can be setup
by the host for the next read. There are several retry levels that
can be attempted until the lost data is recovered or definitely
assumed lost.
This is the port of linux commit
f2cb43c98010 (mtd: spinand: Add read retry support)
Signed-off-by: Cheng Ming Lin <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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The code was ported from linux-6.12. The original continuous reading
support was implemented by Miquel Raynal <[email protected]>
in linux commit 631cfdd0520d (mtd: spi-nand: Add continuous read support).
Here is an original patch description:
--------------------------------------
A regular page read consist in:
- Asking one page of content from the NAND array to be loaded in the
chip's SRAM,
- Waiting for the operation to be done,
- Retrieving the data (I/O phase) from the chip's SRAM.
When reading several sequential pages, the above operation is repeated
over and over. There is however a way to optimize these accesses, by
enabling continuous reads. The feature requires the NAND chip to have a
second internal SRAM area plus a bit of additional internal logic to
trigger another internal transfer between the NAND array and the second
SRAM area while the I/O phase is ongoing. Once the first I/O phase is
done, the host can continue reading more data, continuously, as the chip
will automatically switch to the second SRAM content (which has already
been loaded) and in turns trigger the next load into the first SRAM area
again.
From an instruction perspective, the command op-codes are different, but
the same cycles are required. The only difference is that after a
continuous read (which is stopped by a CS deassert), the host must
observe a delay of tRST. However, because there is no guarantee in Linux
regarding the actual state of the CS pin after a transfer (in order to
speed-up the next transfer if targeting the same device), it was
necessary to manually end the continuous read with a configuration
register write operation.
Continuous reads have two main drawbacks:
* They only work on full pages (column address ignored)
* Only the main data area is pulled, out-of-band bytes are not
accessible. Said otherwise, the feature can only be useful with on-die
ECC engines.
Performance wise, measures have been performed on a Zynq platform using
Macronix SPI-NAND controller with a Macronix chip (based on the
flash_speed tool modified for testing sequential reads):
- 1-1-1 mode: performances improved from +3% (2-pages) up to +10% after
a dozen pages.
- 1-1-4 mode: performances improved from +15% (2-pages) up to +40% after
a dozen pages.
This series is based on a previous work from Macronix engineer Jaime
Liao.
--------------------------------------
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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SkyHigh spinand device has ECC enable bit in configuration register but
it must be always enabled. If ECC is disabled, read and write ops
results in undetermined state. For such devices, a way to avoid raw
access is needed.
Introduce SPINAND_NO_RAW_ACCESS flag to advertise the device does not
support raw access. In such devices, the on-die ECC engine ops returns
error to I/O request in raw mode.
Checking and marking BBM need to be cared as special case, by adding
fallback mechanism that tries read/write OOB with ECC enabled.
This is a port of linux commit
6d9d6ab3a82a (mtd: spinand: Introduce a way to avoid raw access)
Signed-off-by: Takahiro Kuwano <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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We don't have to call spinand_write_enable_op() in spinand_markbad() as
it is called in spinand_write_page().
This is the port of linux commit
c6858779f1f5 (mtd: spinand: Remove write_enable_op() in markbad())
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Add two flags for inserting the Plane Select bit into the column
address during the write_to_cache and the read_from_cache operation.
Add the SPINAND_HAS_PROG_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the write_to_cache operation.
Add the SPINAND_HAS_READ_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the read_from_cache operation.
This is a port of linux commit
ca229bdbef29 (mtd: spinand: Add support for setting plane select bits)
Signed-off-by: Cheng Ming Lin <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Reporting an unclean read from SPI-NAND only when the maximum number
of correctable bitflip errors has been hit seems a bit late.
UBI LEB scrubbing, which depends on the lower MTD device reporting
correctable bitflips, then only kicks in when it's almost too late.
Set bitflip_threshold to 75% of the ECC strength, which is also the
default for raw NAND.
This is a port of linux commit
1824520e7477 (mtd: spinand: set bitflip_threshold to 75% of ECC strength)
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/2117e387260b0a96f95b8e1652ff79e0e2d71d53.1723427450.git.daniel@makrotopia.org
Signed-off-by: Mikhail Kshevetskiy <[email protected]> # U-Boot port
Signed-off-by: Michael Trimarchi <[email protected]>
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This makes the U-Boot SPI NAND driver almost the same as in Linux 6.10.
The only major difference is support of ECC engines. The Linux driver
supports different ECC engines while U-Boot uses on-die ECC only.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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changes:
* Move spinand_check_ecc_status(), spinand_noecc_ooblayout_ecc(),
spinand_noecc_ooblayout_free() and spinand_noecc_ooblayout close
to each other.
* some code formatting
* remove comments not present in linux driver
This aligns the code with Linux 6.10.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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No functional changes, just some refactoring to better match linux
kernel driver.
changes:
* move spinand configuration reading out from spinand_init_cfg_cache()
to separate function spinand_read_cfg()
* move spinand flash initialization to separate function
spinand_init_flash()
* move direct mapping initialization to the end of spinand_init()
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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This aligns the logic to match the Linux kernel implementation.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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Use spinand_to_nand() and spinand_to_mtd() helpers instead of
nanddev_to_mtd() and direct access to spinand structure fields.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
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