| Age | Commit message (Collapse) | Author |
|---|
|
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
SoCFPGA updates for v2025.10:
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762
This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:
* Agilex5 enhancements:
- USB3.1 enablement and DWC3 host driver support
- System Manager register configuration for USB3
- Watchdog timeout increase and SDMMC clock API integration
- dcache handling improvements in SMC mailbox path
- Enable SPL_SYS_DCACHE_OFF in defconfig
* Clock driver improvements:
- Introduce dt-bindings header for Agilex clocks
- Add enable/disable API and EMAC clock selection fixes
- Replace manual shifts with FIELD_GET usage
* DDR updates:
- IOSSM mailbox compatibility check
- Correct DDR calibration status handling
* Device tree changes:
- Agilex5: disable cache allocation for reads
- Stratix10: add NAND IP node
- Enable driver model watchdog
- Enable USB3.1 node for Agilex5
* Config cleanups:
- Simplify Agilex7 VAB defconfig
- Remove obsolete SYS_BOOTM_LEN from N5X VAB config
- Enable CRC32 support for SoCFPGA
- Increase USB hub debounce timeout
Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.
This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
|
|
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
domain, after reset has been asserted by writing a matching reset bit into
register SRCR, it is mandatory to wait 1ms.
Because it is the controller driver which can determine whether or not the
controller is in HSC domain based on its compatible string, add the missing
delay into the controller driver.
This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear
whether S4 is affected as well. This patch does apply the extra delay on
R-Car S4 as well.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Assure the reset is latched and the core is ready for DBI access.
On R-Car V4H, the PCIe reset is asynchronized and does not take
effect immediately, but needs a short time to complete. In case
DBI access happens in that short time, that access generates an
SError. Make sure that condition can never happen, read back the
state of the reset which should turn the asynchronized reset into
synchronized one, and wait a little over 1ms to add additional
safety margin.
Signed-off-by: Marek Vasut <[email protected]>
|
|
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581
Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure
indicates that register 0xf8 should be polled until bit 18 becomes set to 1.
Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set
to 1 in less than 1 ms afterward. The current readl_poll_timeout() break
condition is inverted and returns when register 0xf8 bit 18 is set to 0,
which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y ,
the timing changes just enough for the first readl_poll_timeout() poll to
already read register 0xf8 bit 18 as 1 and afterward never read register
0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe
controller.
Fix this by inverting the poll condition to match the reference manual
initialization sequence.
Signed-off-by: Marek Vasut <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27684
- Add i.MX8 ahab-commit command.
- Add support for flashing board with UUU on imx93_frdm.
- Fix the acces of PFUZE100 regulator desc.
- Add more i.MX6 PWM clock definitions.
- Enable OP-TEE on phytec-imx8m and update documentation.
- Enable PCI host controller on iMX95 19x19 EVK.
[trini: Fixup spacing issues]
Signed-off-by: Tom Rini <[email protected]>
|
|
Adding iMX95/iMX94 support to the dw driver. Follow kernel driver
stype to use flags to distinguish the characteristic of different
platforms.
Signed-off-by: Ye Li <[email protected]>
|
|
Wirting to command register should use PCI_COMMAND not PCI_PRIMARY_BUS
Signed-off-by: Ye Li <[email protected]>
|
|
The dev_err() is used incorrectly and we don't need the driver
to state probe success.
Signed-off-by: Hal Feng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
Replace use of uninitialized variable with the PCI device number
in an error message as this is what we use elsewhere to derive
the PCIe port number. Use ofnode_read_pci_addr() to read the
PCI address of the node and derive the device number from that.
Signed-off-by: Mark Kettenis <[email protected]>
Reported-by: Andrew Goodbody <[email protected]>
|
|
Prepare v2025.10-rc3
|
|
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025
page 4581 Figure 104.3b Initial Setting of PCIEC(example) middle
of the figure indicates that fourth write into register 0x148 [2:0]
is 0x3 or GENMASK(1, 0). The current code writes GENMASK(11, 0)
which is a typo. Fix the typo.
Fixes: be3dd0dc2fd9 ("pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver")
Signed-off-by: Marek Vasut <[email protected]>
|
|
A large number of PCI controllers cannot build without access to some
platform specific header files. Express those requirements in Kconfig as
well.
Signed-off-by: Tom Rini <[email protected]>
|
|
This driver references the SZ_ macros while relying on an indirection
inclusion of <linux/sizes.h>. Add the missing include directly.
Signed-off-by: Tom Rini <[email protected]>
|
|
Many callers of PCI read functions do not check the return value for
error before using the variable that should contain the value read were
there not to be an error. However in the error case this variable is
never assigned to and so will contain uninitialised data.
To provide some certainty as to behaviour in the error case assign a
default value of all bits set.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
|
|
Add R-Car Gen4 PCIe controller support for host mode.
This controller is based on Synopsys DesignWare PCIe. However, this
particular controller has a number of vendor-specific registers, and as
such, requires initialization code, including PHY firmware loading.
The PHY firmware loading is implemented in an entirely generic manner,
by calling a firmware loading script, which the user can configure in
a way they require. This provides the user with flexibility of loading
the PCIe firmware from whichever storage device they need to load it
from.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality. This does change the behavior slightly, as
the dw_pcie_link_set_max_link_width() implementation also programs the
LNKCAP register MLW, this should however be correct and is now aligned
with Linux kernel behavior.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
|
|
Use dw_pcie_link_set_max_link_width() instead of local implementation
of the same functionality. This does change the behavior slightly, as
the dw_pcie_link_set_max_link_width() implementation also programs the
LNKCAP register MLW, this should however be correct and is now aligned
with Linux kernel behavior.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
|
|
Add dw_pcie_link_set_max_link_width() implementation ported from Linux kernel
as of commit 89db0793c9f2 ("PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling").
This is common code which is already duplicated in multiple drivers.
Signed-off-by: Marek Vasut <[email protected]>
|
|
The pcireg base is not assigned to any address, reading the
pcireg base with PS_LINKUP_OFFSET which is incorrect and
giving random values. So update the pcireg base from
devicetree so that we can read the valid PCIE link status
and PHY ready status.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
|
|
Hrushikesh Salunke <[email protected]> says:
TI's AM64 SoC has a single instance of Cadence PCIe Controller. This
series enables support for PCIe in AM64 SoC and to configure it in
Root-Complex mode of operation.
Link: https://lore.kernel.org/r/[email protected]
|
|
TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which
is Cadence PCIe Controller. Add support to configure PCIe0 in Root-
Complex mode of operation.
Signed-off-by: Hrushikesh Salunke <[email protected]>
Reviewed-by: Siddharth Vadapalli <[email protected]>
|
|
Driver uses macro SZ_4G to configure inbound base address register.
The macro is used without including the header file in which it is
defined. Fix this.
Fixes: 59ad5480098 ("pci: Add TI K3 Cadence PCIe Controller")
Signed-off-by: Hrushikesh Salunke <[email protected]>
Reviewed-by: Siddharth Vadapalli <[email protected]>
|
|
Jiaxun Yang <[email protected]> says:
This is a huge series which promoted MIPS/Boston target into a
usable state, with fixes to drivers and general framework issues
I found in this process.
I also converted the target to OF_UPSTREAM.
This target is covered by QEMU, to test on QEMU:
```
make boston64r6el_defconfig
make
qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic
```
Link: https://lore.kernel.org/r/[email protected]
|
|
For MIPS we are always looking gd->dram in virtual address so
PCI_MAP_SYSTEM_MEMORY should always be enabled.
If in future we ever want to make it physical we have to set
ARCH_MAP_SYSMEM.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
|
|
Boston has a very limited memory range for PCI controllers, where
1MB can't easily fit into it.
Make alignment boundary of PCI memory resource allocation a Kconfig
option and default to 0x10000 for boston.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
|
|
Probe size of ecam from devicetree properly and cap accessible
bus number accorading to ecam region size to ensure we don't go
beyond hardware address space.
Also disable all interrupts to ensure errors are handled silently.
Signed-off-by: Jiaxun Yang <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
|
|
Legacy PCI devices, like qemu's Bochs VGA device, are allowed to have
prefetchable 32-bit BARs, while PCIe devices are not allowed to have
32-bit prefetchable BARs. Typically prefetchable BARs are 64-bit and
typically the prefetch MMIO window is also 64-bit and placed above
4GiB, as it's the case on qemu sbsa-ref.
Currently the U-Boot code assumes that prefetchable BARs are
64-bit BARs and always tries to assign them into the prefetch
MMIO window.
When a 32-bit BAR is marked as prefetch, but the prefetch area is
not within the first 4GiB of the address space, then downgrade the
BAR and place it in the non-prefetch MMIO window.
For prefetch BARs there's no downside on being placed in non prefetch
MMIO areas, besides the possible slower performance when a driver tries
to map it Write-Combine.
TEST: Fixes pci_auto on QEMU sbsa-ref fails to autoconfigure BAR0.
Signed-off-by: Patrick Rudolph <[email protected]>
|
|
One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0
on this port represents the controller itself and bus 1 represents
the external PCIe device.
If multiple PCIe controllers are probed in U-Boot, U-Boot will use
bus numbers greater than 2 as input parameters. Therefore, we should
convert the BDF bus number to either 0 or 1 by subtracting the
offset by controller->seq_.
Signed-off-by: Sam Shih <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
|
|
Simon Glass <[email protected]> says:
The current UPL spec[1] has been tidied up and improved over the last
year, since U-Boot's original UPL support was written.
This series includes some prerequisite patches needed for the real UPL
patches. It is split from [2]
[1] https://github.com/UniversalPayload/spec/tree/3f1450d
[2] https://patchwork.ozlabs.org/project/uboot/list/?series=438574&state=*
Link: https://lore.kernel.org/r/[email protected]
|
|
Add this information to the handoff structure so that it is available to
U-Boot proper. Update bochs and the video handoff.
Signed-off-by: Simon Glass <[email protected]>
|
|
Add support for the PCIe busses on Qualcomm platforms,
by using the pcie_dw_common infrastructure.
The driver is based on the Linux driver but only supporting
the "1_9_0" and compatible platforms like:
- sa8540p
- sc7280
- sc8180x
- sc8280xp
- sdm845
- sdx55
- sm8150
- sm8250
- sm8350
- sm8450
- sm8550
- sm8650
- x1e80100
But it has only been tested on:
- sc7280
- sm8550
- sm8650
- x1e80100
It supports setting the IOMMU SID table for supported platforms.
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
|
|
Add PCIe config space capability search function specific for
the host controller, which are bridges *to* PCI devices but
are not PCI devices themselves.
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
|
|
Prepare v2025.01-rc5
|
|
There are difference between upstream DT and the old DT
in terms of reg base, reset gpio and syscon. Make the driver
compatible with upstream DT.
Tested-by: Anand Moon <[email protected]>
Tested-by: E Shattow <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
|
|
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Patrick Rudolph <[email protected]> says:
Based on the existing work done by Simon Glass this series adds
support for booting aarch64 devices using ACPI only.
As first target QEMU SBSA support is added, which relies on ACPI
only to boot an OS. As secondary target the Raspberry Pi4 was used,
which is broadly available and allows easy testing of the proposed
solution.
The series is split into ACPI cleanups and code movements, adding
Arm specific ACPI tables and finally SoC and mainboard related
changes to boot a Linux on the QEMU SBSA and RPi4. Currently only the
mandatory ACPI tables are supported, allowing to boot into Linux
without errors.
The QEMU SBSA support is feature complete and provides the same
functionality as the EDK2 implementation.
The changes were tested on real hardware as well on QEMU v9.0:
qemu-system-aarch64 -machine sbsa-ref -nographic -cpu cortex-a57 \
-pflash secure-world.rom \
-pflash unsecure-world.rom
qemu-system-aarch64 -machine raspi4b -kernel u-boot.bin -cpu cortex-a72 \
-smp 4 -m 2G -drive file=raspbian.img,format=raw,index=0 \
-dtb bcm2711-rpi-4-b.dtb -nographic
Tested against FWTS V24.03.00.
Known issues:
- The QEMU rpi4 support is currently limited as it doesn't emulate PCI,
USB or ethernet devices!
- The SMP bringup doesn't work on RPi4, but works in QEMU (Possibly
cache related).
- PCI on RPI4 isn't working on real hardware since the pcie_brcmstb
Linux kernel module doesn't support ACPI yet.
Link: https://lore.kernel.org/r/[email protected]
|
|
These header files presumably duplicate things already in the U-Boot
devicetree. For now, bring them in to get the ASL code and ACPI table
code to compile.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Patrick Rudolph <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Matthias Brugger <[email protected]>
Cc: Matthias Brugger <[email protected]>
Cc: Peter Robinson <[email protected]>
Cc: Tom Rini <[email protected]>
|
|
Add support for the Cadence PCIe Controller present on TI's K3 SoCs.
This driver is an adaptation of the Linux driver.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
Rename this function to indicate that it refers to any xPL phase.
Signed-off-by: Simon Glass <[email protected]>
|
|
Add support for upstream linux split PCIe node.
Upstream linux have an alternative way to declare PCIe nodes that splits
them in dedicated nodes for each line instead of putting them all in one
node.
Detect this by checking if the mediatek,generic-pciecfg node is passed
as it's used to reference the common address for all the PCIe lines.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Set pcie-phy optional for PCIe gen3. MT7988 doesn't require it and
making it mandatory prevent the driver to correctly probe.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Add MediaTek GEN3 PCIe controller support for filogic silicon.
This is adapted from the Linux version of the driver.
Signed-off-by: John Crispin <[email protected]>
[ fix minor problems, fix checkpatch errors ]
Signed-off-by: Christian Marangi <[email protected]>
|
|
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
Remove <common.h> from this driver directory and when needed
add missing include files directly.
Reviewed-by: Heiko Schocher <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
|
|
Since now we have the modern pcie_dw_imx.c driver for iMX SoCs,
encourage people to switch to that for any further new iMX SoC support
or even for the older iMX6 SoCs too.
Suggested-by: Peter Robinson <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
|
|
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Tested-by: Tim Harvey <[email protected]> #imx8mp-venice*
Tested-by: Adam Ford <[email protected]> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
|
