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Add initial pin control tables for the Renesas R-Car X5H R8A78000 SoC.
This SoC is the first one which includes custom DRV register handling,
different from previous generations due to change in DRV register bit
layout.
Signed-off-by: Huy Bui <[email protected]>
Signed-off-by: Khanh Le <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The upcoming Renesas R-Car Gen5 uses different mapping of bits in DRV
control register, which is incompatible with existing DRV register bit
mapping. Add .set_drive_strength callback into sh_pfc_soc_operations
and call it from sh_pfc_pinconf_set(), to allow each SoC specific PFC
driver to implement replacement .set_drive_strength. Make the current
sh_pfc_pinconf_set_drive_strength() non-static, rename it with rcar_
prefix, and pass it as .set_drive_strength for existing PFC drivers.
This is a preparatory patch for R-Car Gen5, no functional change.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
[Marek: Consistently use .set_drive_strength() and pass exisiting
sh_pfc_pinconf_set_drive_strength() as its parameter for
all PFC drivers. Rewrite commit message.]
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Show bit position in config write debug log, which is helpful for cases
where the p port setting is applied at the exact p bit position.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Unsplit the string
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Fix Kconfig entry indent to be always consistently indented with
leading tabs, never with leading spaces. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.
Signed-off-by: Danila Tikhonov <[email protected]>
Co-developed-by: Jens Reidel <[email protected]>
Signed-off-by: Jens Reidel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6350 SoC, with support for special pins.
Correct pin configuration is required for working debug UART and eMMC/SD
cards.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
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There's no WEST, SOUTH or NORTH in sc7280 pinctrl. Fix the offset of the
ufs_reset pin.
Fixes: 51ec7fdb64b ("pinctrl: qcom: add sc7280 pinctrl driver")
Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add a pinctrl driver for the TLMM block found in the SDM670 SoC.
Signed-off-by: David Wronek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.
The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.
Signed-off-by: Naman Trivedi <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Acked-by: Senthil Nathan Thangaraj <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
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meson_gpio_get() always assumes gpio is configured to input mode. This
is incorrect and breaks `gpio toggle` command:
gpio: pin aobus-banks2 (gpio 2) value is 0
Warning: value of pin is still 1
Fix it by adding the logic to handle both input and output mode.
Fixes: 2009a8d03fe5 ("pinctrl: meson: add GPIO support")
Signed-off-by: Yang Xiwen <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Define the daisy register offset for i.MX94 at 0x608 within the iomuxc
register space. This enables correct pad selection for daisy chain
configuration on i.MX94 platforms.
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
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It's common that UARTs are bound and probed before U-Boot relocation, in
which case the UART's pincontroller and pinconfig must be probed first.
Let's apply DM_FLAG_PRE_RELOC to the driver, allow it to bind before
relocation.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Prepare v2025.10-rc4
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In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to
rzg2l_selector_decode fails then the variable pin may not have been
assigned to. Remove the use of pin from the error message. Also update
the error message to show the invalid selector used instead of port
which will be the error code returned.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Prepare v2025.10-rc3
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In zynqmp_pinconf_set if param is PIN_CFG_IOSTANDARD or
PIN_CONFIG_POWER_SOURCE and zynqmp_pm_pinctrl_get_config returns an
error then value will not be assigned to when its value is tested to be
not equal to arg. Add code to only test value not equal to arg if ret is
false.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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In zynqmp_pinctrl_prepare_func_groups if called with func->ngroups == 0
then ret will not be assigned to before its value is returned on exit.
Initialise ret to ensure it is always valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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In s5pxx18_pinctrl_set_state testing count to be negative will always
fail as count is unsigned despite receiving the return value of a
function that returns an int. Change count and idx to be of type int to
allow the test to work as expected and remove the need for any implicit
casts. Also change pin to be u32 which is what all called functions
expect.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Add pinmux for the VCD input to use the HSYNC signal.
Signed-off-by: Stanley Chu <[email protected]>
Signed-off-by: Jim Liu <[email protected]>
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In stmfx_read_reg there is duplicated code to detect ret < 0 and return
ret if so. Remove one version of it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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In single_read there is a switch block with a default label. All cases
in the switch block, including the default, return directly. So any code
following the switch block is unreachable. Remove the unreachable code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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A few pinctrl drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27364
Quite a few Smatch issues reported by Andrew, and the LMB allocation
fix.
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The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The Linux pinctrl-sx150 was originally written as a GPIO driver
and fully rewritten by me as a Pinctrl driver and extended by
other contributors.
Fixup the Copyright header style and correctly report the
Copyright headers from the Linux driver.
Signed-off-by: Neil Armstrong <[email protected]>
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Fixes: 5451504256d3 ("pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver")
Signed-off-by: Chali Anis <[email protected]>
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The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.
Add the values for the primary and secondary pin controller on the A523.
Signed-off-by: Andre Przywara <[email protected]>
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The logic was updated without modifying the comment above it
Fixes: 72b8c6d1ebf ("pinctrl: don't fall back to pinctrl_select_state_simple()")
Signed-off-by: Philip Molloy <[email protected]>
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The SoC pads of TH1520 are separated into three groups (AP 1, AP 2 and
AON) controlled by independent pin controllers. This patch ports their
driver from Linux kernel with most code for setting pinconf and pinmux
kept as is.
The dt-binding of TH1520 pin controller uses a schema where pins to
configure are specfied as strings and looked up at runtime, which the
generic pinctrl helpers of U-Boot cannot parse, thus a customized
set_state() callback is implemented to parse pinconfig nodes and setup
the configuration.
Signed-off-by: Yao Zi <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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The commit e8a9521e649f
("vf500/vf610: synchronise device trees with linux")
has synchronized U-Boot's DTS with v5.19 Linux kernel.
It turned out that in Linux's upstream iomuxc node description the
'fsl,mux_mask' was missing, so the U-Boot's pinctrl driver for NXP's
Vybrid SoC was not working properly.
As by default the mux mask was set to 0, for example the vf610 based
boards (like BK4) were bricked, due to misconfiguration of gpio at
early boot stage.
The fix for all NXP eligible boards is to define .mux_mask field for
soc specific *pinctrl_soc_info structure and use it directly in pinctrl
MMIO driver, without the need to read the "fsl,mux_mask" property from
device tree.
This change brings the NXP's pinctrl driver in U-Boot closer to Linux
upstream one.
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Peng Fan <[email protected]> #for i.MX8ULP
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Add pinctrl driver for the TLMM block found in the ipq5424 SoC.
Signed-off-by: Varadarajan Narayanan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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implement a driver to use semtech pinctrl and
gpio expander, this driver is adapted from a
existent linux driver that is written by
Gregory Bean <[email protected]>.
Signed-off-by: Anis Chali <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The logic in the core reads the nr_pins of the controller and uses it as
the index of the first pin in the bank (pin_base) it currently parses.
It then increments the number of pins in the controller before going to
the next bank.
This works "fine" for controllers where nr_pins isn't defined in their
rockchip_pin_ctrl struct as it defaults to 0. However, when it is
already set, it'll make the index pin of each bank offset by the number
in nr_pins declared in the struct at initialization, and it'll keep
growing while adding banks, which means the total number of pins in the
controller will be misrepresented.
Additionally, U-Boot proper may probe this driver twice (pre-reloc and
true proper) and not reset nr_pins of the controller in-between meaning
the second probe will have an offset of the actual correct nr_pins.
Instead, let's just store locally the number of pins in the controller
and make sure it's reset between probes.
Finally, this stops modifying a const struct which will soon be
triggering a CPU abort at runtime.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This patch adds SCMI pin control protocol support to make the pin
controller driver based on SCMI, such as
drivers/pinctrl/nxp/pinctrl-imx-scmi.c, can be bound to the SCMI agent
device whose protocol id is 0x19.
Signed-off-by: Alice Guo <[email protected]>
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This patch provides a pinctrl driver based on SCMI pin control protocol.
Currently, only the PINCTRL_CONFIG_SET command is implemented.
Signed-off-by: Ranjani Vaidyanathan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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Caleb Connolly <[email protected]> says:
Introduce a new event to signal that the live tree has been built,
allowing boards to perform fixups on the tree before devices are bound.
Crucially this allows for devices to be enabled or disabled, but also
allows for properties that are parsed during the bind stage to be
modified (such as dr_mode for dwc3).
With this in place, mach-snapdragon is switched over to use the event
and some hacky U-Boot specific DT overrides (which had to be undone
prior to booting an image) are removed in favour of fixing up the
livetree (which is not passed on to further boot stages).
Finally, some minor fixes are made for the QCM2290 RB1 board, the sdcard
is enabled and it now uses USB host mode in U-Boot like it's bigger
sibling the RB2.
Link: https://lore.kernel.org/r/[email protected]
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