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The architecture is currently unmaintained, remove.
Cc: Benjamin Matthews <[email protected]>
Cc: Chong Huang <[email protected]>
Cc: Dimitar Penev <[email protected]>
Cc: Haitao Zhang <[email protected]>
Cc: I-SYST Micromodule <[email protected]>
Cc: M.Hasewinkel (MHA) <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Martin Strubel <[email protected]>
Cc: Peter Meerwald <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Valentin Yakovenkov <[email protected]>
Cc: Wojtek Skulski <[email protected]>
Cc: Wojtek Skulski <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This patch adds support for the QSPI IP found in stm32f7 devices.
Signed-off-by: Michael Kurz <[email protected]>
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Dropped becuase
- driver not used any board.
- no dm conversion.
Cc: Angelo Dureghello <[email protected]>
Cc: Richard Retanubun <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Angelo Dureghello <[email protected]>
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Dropped becuase
- driver and related configs not used any board.
- no dm conversion.
Cc: Heiko Schocher <[email protected]>
Cc: Sergey Kostanbaev <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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armada100_spi.c and related env is zapping becuase
of "no DM conversion".
Cc: Ajay Bhargav <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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armada100_spi.c, related config options and related codes
are zapping becuase of "no DM conversion".
Cc: Werner Pfister <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The SPI IP core in the Marvell Armada 3700 is similar to the one in the
other Armada SoCs. But the differences are big enough that it makes
sense to introduce a new driver instead of cluttering the old
kirkwood driver with #ifdef's.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Kostya Porotchkin <[email protected]>
Cc: Wilson Ding <[email protected]>
Cc: Victor Gu <[email protected]>
Cc: Hua Jing <[email protected]>
Cc: Terry Zhou <[email protected]>
Cc: Hanna Hawa <[email protected]>
Cc: Haim Boot <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This driver implements SPI protocol in master mode to communicate
with the SPI device connected on SPI bus. It handles /CS explicitly
by controlling respective pin as gpio ('cs-gpios' property in dt node)
and uses PIO mode for SPI transaction. It is configurable based
on driver-model only.
Cc: Jagan Teki <[email protected]>
Signed-off-by: Purna Chandra Mandal <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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This patch add a compatible spi driver for ath79 series SOC.
Signed-off-by: Wills Wang <[email protected]>
Reviewed-by: Thomas Chou <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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This is the normal Tegra SPI driver modified to work with the
QSPI controller in Tegra210. It does not do 2x/4x transfers
or any other QSPI protocol.
Signed-off-by: Yen Lin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.
=> sf probe
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB
=> mw.b 0x100 0xCC 0x1000000
=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s
=> sf read 0x3000000 0x0 0x1000000
device 0 whole chip
SF: 16777216 bytes @ 0x0 Read: OK
=> cmp.b 0x3000000 0x100 0x1000000
Total of 16777216 byte(s) were the same
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Michal Simek <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass <[email protected]>
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Use object files as incresing alphabetic order, so-that it's
easy for readability.
Signed-off-by: Jagan Teki <[email protected]>
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Zap oc_tiny_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Thomas Chou <[email protected]>
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Zap ftssp010_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Kuo-Jung Su <[email protected]>
Cc: Axel Lin <[email protected]>
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Zap andes_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <[email protected]>
Cc: Macpaul Lin <[email protected]>
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Move the Freescale DSPI driver over to driver model.
Signed-off-by: Haikun Wang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Albert ARIBAUD (3ADEV) <[email protected]>
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This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
drivers is not possible.
This driver is very loosely based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver, as we don't support interrupts and DMA right now.
This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Pavel Machek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Jagannadha Sutradharudu Teki <[email protected]>
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This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).
As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.
Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Vince Bridgers <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Jagannadha Sutradharudu Teki <[email protected]>
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This converts the Tegra SPI drivers to use driver model. This is tested
on:
- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore
(not tested on Tegra124)
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Add a new implementation of soft_spi that uses device tree to specify the
GPIOs. This will replace soft_spi_legacy for boards which use driver model.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Reserve the 'normal' name for use by driver model, and rename the old
driver so that it is clear that it is for 'legacy' drivers only.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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U-Boot includes a SPI emulation driver already but it is not explicit, and
is hidden in the SPI flash code.
Conceptually with sandbox's SPI implementation we have a layer which
creates SPI bus transitions and a layer which interprets them, currently
only for SPI flash. The latter is actually an emulation, and it should be
possible to add more than one emulation - not just SPI flash.
Add a SPI emulation uclass so that other emulations can be plugged in to
support different types of emulated devices on difference buses/chip
selects.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add a uclass which provides access to SPI buses and includes operations
required by SPI.
For a time driver model will need to co-exist with the legacy SPI interface
so some parts of the header file are changed depending on which is in use.
The exports are adjusted also since some functions are not available with
driver model.
Boards must define CONFIG_DM_SPI to use driver model for SPI.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
(Discussed some follow-up comments which will address in future add-ons)
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This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev <[email protected]>
Cc: [email protected]
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Add Freescale QSPI driver support for VF610.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Chao Fu <[email protected]>
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The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.
NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.
Signed-off-by: Kuo-Jung Su <[email protected]>
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
CC: Tom Rini <[email protected]>
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This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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This adds a SPI framework for people to hook up simulated SPI clients.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Porter <[email protected]>
Signed-off-by: Sourav Poddar <[email protected]>
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <[email protected]>
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Conflicts:
drivers/spi/tegra20_sflash.c
include/fdtdec.h
lib/fdtdec.c
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Add driver for tegra114 SPI controller. This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.
Signed-off-by: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Add a common interface to fdt based SPI drivers. Each driver is
represented by a table entry in fdt_spi_drivers[]. If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.
Signed-off-by: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.
Signed-off-by: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.
This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.
Signed-off-by: Bernie Thompson <[email protected]>
Signed-off-by: Duncan Laurie <[email protected]>
Signed-off-by: Bill Richardson <[email protected]>
Signed-off-by: Vadim Bendebury <[email protected]>
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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At present it is difficult to extend the SPI structure since all
drivers allocate it themselves, and few of them zero all fields. Add
a new function spi_alloc_slave() which can be used by SPI drivers
to perform this allocation, and thus ensure that all drivers can
better cope with SPI structure changes.
Signed-off-by: Simon Glass <[email protected]>
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Spi driver for bf60x is different from old one, so implement a new
driver for it.
Signed-off-by: Scott Jiang <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
Signed-off-by: Bob Liu <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This patch adds SPI driver for EXYNOS.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Padmavathi Venna <[email protected]>
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Hatim Ali <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: [email protected]
Signed-off-by: Minkyu Kang <[email protected]>
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This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.
Tested with MCF5270 which have 4 chip selects.
Activate by #define CONFIG_CF_QSPI in board config.
Signed-off-by: Richard Retanubun <[email protected]>
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The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*"
(sha1: edffa63d3d6e76991998789f9fcbaa483731ca65)
renamed tegra2_spi.c to tegra_spi.c
and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze"
(sha1: d978780b2e676c005460cd561f4f15b5220bdf49)
has wrongly resolved confict.
This patch fix it.
Signed-off-by: Michal Simek <[email protected]>
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* 'master' of git://git.denx.de/u-boot-microblaze:
microblaze: Wire up SPI driver
spi: microblaze: Adds driver for Xilinx SPI controller
microblaze: intc: Clear interrupt code
microblaze: Call serial multi initialization
microblaze: Move __udelay implementation
microblaze: Remove extern from board.c
microblaze: Wire up dts configuration
fdt: Add board specific dts inclusion
microblaze: Move individual board linker scripts to common script in cpu tree.
microblaze: Add gpio.h
microblaze: Add missing undefs for UBI and UBIFS
microblaze: Expand and correct configuration comments
microblaze: Enable ubi support
microblaze: Avoid compile error on systems without cfi flash
microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION
Conflicts:
drivers/spi/Makefile
Signed-off-by: Wolfgang Denk <[email protected]>
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This is an improved version of the driver patch original
submitted by Graeme Smecher <[email protected]>
The changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
use the new register struct instead
- move default SPI controller configuration from
spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP
Come from:
http://patchwork.ozlabs.org/patch/71797/
Signed-off-by: Stephan Linz <[email protected]>
Tested-by: Michal Simek <[email protected]>
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In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.
Signed-off-by: Tom Warren <[email protected]>
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This driver supports SPI on Tegra2, running at 48MHz.
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Detlev Zundel <[email protected]>
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