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Add new driver to support NXP XSPI controller for NOR and NAND flash.
XSPI controller also uses a programmable sequence engine to provide
flexibility to support existing and future memory devices. It supports
single, dual, quad, octal modes of operation.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
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To reduce SPL size, make it possible to exclude designware driver,
while keeping it enabled in the main u-boot.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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This patch ports the Cadence xSPI controller driver from
the Linux kernel. The controller supports three operating modes:
1. ACMD (Auto Command) mode
- Includes PIO and CDMA submodes.
- CDMA mode uses linked descriptors for high-performance,
low-overhead operation.
- PIO mode is suitable for simple, single-command transactions.
2. STIG (Software Triggered Instruction Generator) mode
- Issues low-level 128-bit instructions to memory.
- Uses the Slave DMA interface for data transfers.
3. Direct mode
- Enables direct data access through the slave interface
without commands.
Currently, only the STIG work mode is enabled. Additional modes will be
supported in future updates.
At the same time, also enabling the kconfig option for xSPI driver.
This driver has been ported and functionally verified on the Intel Simics
platform. It is intended for evaluation and experimental use at this stage.
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add STM32 OSPI driver, it supports :
- support sNOR / sNAND devices.
- Two functional modes: indirect (read/write) and memory-mapped (read).
- Single-, dual-, quad-, and octal-SPI communication.
- Single data rate (SDR).
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Add Airoha SPI NAND driver to permit usage of attached SNAND on the
Airoha AN7581 SoC. While SPI controller supports DMA transation, due to
U-Boot limitation we currently limit it to single command in Manual
mode.
Signed-off-by: Christian Marangi <[email protected]>
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This adds support for the ADI-specific SPI driver present in the ADI
SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block
that uses the Cadence driver. Both may be used at once with appropriate
pin muxing configuration.
Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Angelo Dureghello <[email protected]>
Signed-off-by: Angelo Dureghello <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Co-developed-by: Piotr Wojtaszczyk <[email protected]>
Signed-off-by: Piotr Wojtaszczyk <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
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Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.
Update the comment in bootstage to refer to this symbol, instead of
SPL_
Signed-off-by: Simon Glass <[email protected]>
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Add spi nor flash controller driver for cv1800b SoC
Signed-off-by: Kongyang Liu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver
framework and accommodate to lack of ioread32_rep/iowrite32_rep.
Based on Linux version 6.6-rc4
Signed-off-by: Igor Prusov <[email protected]>
Signed-off-by: Martin Kurbanov <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
[trini: Drop <common.h> as it's not needed]
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The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Introduce Socionext F_OSPI controller driver. This controller is used to
communicate with slave devices such as SPI flash memories. It supports
4 slave devices and up to 8-bit wide bus, but supports master mode only.
This driver uses spi-mem framework for SPI flash memory access, and
can only operate indirect access mode and single data rate mode.
Signed-off-by: Kunihiko Hayashi <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli <[email protected]>
Signed-off-by: Naga Sureshkumar Relli <[email protected]>
Signed-off-by: Padmarao Begari <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
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Add Nuvoton NPCM BMC Peripheral SPI controller driver.
NPCM750 include two general-purpose SPI interface.
Signed-off-by: Jim Liu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This patch adds support for spi-mem controller found on newer MediaTek SoCs
This controller supports Single/Dual/Quad SPI mode.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Daniel Golle <[email protected]>
Signed-off-by: SkyLake.Huang <[email protected]>
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Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.
There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.
- SPI1: Play the role of a SPI Master controller. Or, there is a
dedicated path for HOST(X86) to access its BIOS flash mounted
under BMC. spi-aspeed-smc.c implements the control sequence when
SPI1 is a SPI master.
- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
mounted under it are for pure storage purpose.
ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
The address length is decided by FMC04[2:0].
- Command mode: SPI controller can send command and address
automatically when CPU read/write the related remapped
or decoded address area. The command used by this mode
can be configured by FMC10/14/18[23:16]. Also, the
address length is decided by FMC04[2:0]. This mode will
be implemented in the following patch series.
- User mode: It is a traditional and pure SPI operation, where
SPI transmission is controlled by CPU. It is the main
mode in this patch.
Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.
This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.
Signed-off-by: Chin-Ting Kuo <[email protected]>
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Add support for cadence ospi driver for Versal platform. This driver
provides support for DMA read operation which utilizes cadence qspi
driver.
If "cdns,is-dma" DT property is specified use dma for read operation
from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in
cadence_ospi_versal driver add a weak function defination in
cadence_qspi driver.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash.
Signed-off-by: Nick Hawkins <[email protected]>
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Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master
controller driver using SPI-MEM interface.
The FIU supports single, dual or quad communication interface.
The FIU controller driver provides flash access in UMA(User
Mode Access) mode by using an indirect address/data mechanism.
the dts node is followed upstream kernel dts name.
Signed-off-by: Jim Liu <[email protected]>
Signed-off-by: Stanley Chu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
[Jagan: fixed the Kconfig, Makefile order]
Signed-off-by: Jagan Teki <[email protected]>
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IPROC qspi driver supports both BSPI and MSPI modes.
Signed-off-by: Rayagonda Kokatanur <[email protected]>
Signed-off-by: Bharat Gooty <[email protected]>
Acked-by: Rayagonda Kokatanur <[email protected]>
Signed-off-by: Roman Bacik <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add a driver for the SPI controller integrated on Apple SoCs.
This is necessary to support the keyboard on Apple Silicon laopts
since their keyboard uses an Apple-specific HID over SPI protocol.
Signed-off-by: Mark Kettenis <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested on: Macbook Air M1
Tested-by: Simon Glass <[email protected]>
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This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The driver depends on DM_SPI and if it's not available (e. g. in SPL),
then we should not try to build it as this will fail.
Signed-off-by: Frieder Schrempf <[email protected]>
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This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar <[email protected]>
Signed-off-by: Masami Hiramatsu <[email protected]>
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Add a driver for Macronix SPI controller IP.
This patch referred from linux spi-mxic.c. The difference from the
linux version is described here.
1. To adapt uboot spi framework, modify some functions naming.
2. Remove the incompatible functions of Uboot.
3. Add dummy byte recalculattion function to support dummy buswidth
not align data buswidth operation.(ex: 1-1-4, 1-1-8)
4. Add Octal mode support.
Signed-off-by: Zhengxun <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
[jagan: fixed file permission, comment line, kconfig]
Signed-off-by: Jagan Teki <[email protected]>
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This patch adds support for MTK SPI NOR controller, which you
can see on mt7622 & mt7629.
1. This controller is designed only for SPI NOR. We can't adjust
its bus clock dynamically. Set clock in dts instead.
2. This controller only supports 1-1-1 write mode.
3. Remove mtk_snor_match_read() since upper SPI-MEM layer already
handles command.
4. sf read/write/update commands are tested with this driver.
Signed-off-by: SkyLake.Huang <[email protected]>
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This patch adds spi controller support for MediaTek MT7620 SoC.
The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each register group.
Appearently these two register groups cannot operates simulataneously so
they are implemented as one controller.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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Add SPI Flash controller driver for Cortina Access
CAxxxx SoCs
Signed-off-by: Pengpeng Chen <[email protected]>
Signed-off-by: Alex Nemirovsky <[email protected]>
CC: Vignesh R <[email protected]>
CC: Tom Rini <[email protected]>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s.
Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW.
FIFO and Block modes are supported, no support for DMA mode is planned.
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Luka Kovacic <[email protected]>
Cc: Luka Perkov <[email protected]>
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Adds support for SPI controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams <[email protected]>
Signed-off-by: Suneel Garapati <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
Cc: Jagan Teki <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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This converts the following to Kconfig:
CONFIG_CADENCE_QSPI
Signed-off-by: Tom Rini <[email protected]>
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This change allows more fine tuning of driver model based SPI support in
SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
support in SPL and TPL via Kconfig option.
Before this change it was necessary to use:
/* SPI Flash Configs */
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_SPI_FLASH_MTD
#endif
in the ./include/configs/<board>.h, which is error prone and shall be
avoided when we strive to switch to Kconfig.
The goal of this patch:
Provide distinction for DM_SPI support in both U-Boot proper and SPL (TPL).
Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
still support non DM driver.
Another use case is the conversion of non DM/DTS SPI driver to support
DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the
distinction is needed in Kconfig (also if SPL version of the driver
supports OF_PLATDATA).
In the end of the day one would have to support following use cases (in
single driver file - e.g. mxs_spi.c):
- U-Boot proper driver supporting DT/DTS
- U-Boot proper driver without DT/DTS support (deprecated)
- SPL driver without DT/DTS support
- SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
run full blown DT/DTS)
- SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
environment with no fitImage and OF_LIBFDT support).
Some boards do require SPI support (with DM) in SPL (TPL) and some only
have DM_SPI{_FLASH} defined to allow compiling SPL.
This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI)
and provides corresponding defines in Kconfig.
Signed-off-by: Lukasz Majewski <[email protected]>
Tested-by: Adam Ford <[email protected]> #da850-evm
Signed-off-by: Hou Zhiqiang <[email protected]>
[trini: Fixup a few platforms]
Signed-off-by: Tom Rini <[email protected]>
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- Deadline for DM migration already passed by months.
- Sent couple of zap patches and
- No response on dm conversation
hence removed the driver.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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sh_spi driver is deprecated, no active updates and
no board user, hence dropped the same.
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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lpc32xx_ssp driver is deprecated, no active updates
and no board user, hence dropped the same.
Cc: Vladimir Zapolskiy <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.
The port was straightforward:
- remove the interrupt handling and the completion by busy polling the
controller
- remove locks
- move the setup of the memory windows into claim_bus()
- move the setup of the speed into set_speed()
- port the device tree bindings from the original fspi_probe() to
ofdata_to_platdata()
There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.
This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Kuldeep Singh <[email protected]>
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Since u-boot has added the spi-mem framework and replaced
the spi-nor framework, the mtk_qspi is no longer compatible
with the new spi-nor driver.
Remove this driver along with replacing config item
with new mtk spi-nor driver.
Signed-off-by: Weijie Gao <[email protected]>
[jagan: squash related changes and update commit message]
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This patch adds spi-mem driver for MediaTek MT7629 SoC
to access SPI-NOR and SPI-NAND flashes.
Signed-off-by: Weijie Gao <[email protected]>
[jagan: squash MAINTAINERS file]
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This patch adds SiFive SPI driver. The driver is 100% DM driver
and it determines input clock using clk framework.
The SiFive SPI block is found on SiFive FU540 SOC and is used to
access flash and MMC devices on SiFive Unleashed board.
This driver implementation is inspired from the Linux SiFive SPI
driver available in Linux-5.2 or higher and SiFive FSBL sources.
Signed-off-by: Bhargav Shah <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add SPI controller driver implemented in Socionext UniPhier SoCs.
This controller has the SPI master mode only.
Signed-off-by: Kunihiko Hayashi <[email protected]>
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Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.
Signed-off-by: Tudor Ambarus <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add SPI driver support for STM32MP SoCs family.
Signed-off-by: Patrice Chotard <[email protected]>
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Now that all boards using TI QSPI have moved to DM and DT, drop non DM
code completely.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
[jagan: update MIGRATION.txt, rebase config_whitelist.txt]
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Now the same SPI controller driver is reusable in all Allwinner
SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c
which eventually look like a common sunxi driver.
Also update the function, variable, structure names in driver from
sun4i into sunxi.
Signed-off-by: Jagan Teki <[email protected]>
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Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.
Signed-off-by: Vignesh R <[email protected]>
Tested-by: Simon Goldschmidt <[email protected]>
Tested-by: Stefan Roese <[email protected]>
Tested-by: Horatiu Vultur <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]> #zynq-microzed
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This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.
Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write.
Signed-off-by: Lars Povlsen <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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This patch adds MT7629 qspi driver for accessing SPI NOR flash.
Signed-off-by: Guochun Mao <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC.
This driver, ported from the Linux meson-spi-spifc driver, add support
for this controller on the Amlogic Meson GX SoCs in U-Boot.
Tested-by: Jerome Brunet <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
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This patch adds the SPI driver for the MediaTek MT7688 SoC (and
derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
Gateway additionally with an SPI NAND on CS1.
Note that the SPI controller only supports a max transfer size of 32
bytes. This driver implementes a workaround to enable bigger xfer
sizes to speed up the transfer especially for the SPI NAND support.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Piotr Dymacz <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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This is the PR for SPI-NAND changes along with few spi changes.
[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini <[email protected]>
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