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This information help with debugging issues with uart.
Signed-off-by: Michal Simek <[email protected]>
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This change enables to change baudrate on command line.
Signed-off-by: Michal Simek <[email protected]>
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Each board with defines it's own set of values. If we do not define
CONFIG_MVGBE_PORTS we will hit following error:
mvgbe.c: In function 'mvgbe_initialize':
mvgbe.c:700:34: error: 'CONFIG_MVGBE_PORTS' undeclared (first use in this function)
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
This patch fixes above described problem.
Signed-off-by: Luka Perkov <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
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As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.
Signed-off-by: Simon Glass <[email protected]>
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On x86 we use CMOS RAM to read and write some settings. Add basic support
for this, including access to registers 128-255.
Signed-off-by: Simon Glass <[email protected]>
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Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.
Signed-off-by: Ruchika Gupta <[email protected]>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <[email protected]>
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Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <[email protected]>
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commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
"reg" property should be parsed from the dtb (as was previously the
case).
With this patch i can successfully network boot my jetson tk1
Signed-off-by: Sjoerd Simons <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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Some machines are very slow to scroll their displays. To cope with this,
support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows
the display to operate at an acceptable speed by scrolling 5 lines at
a time.
This same option is available for LCDs so when these systems are unified
this code can be unified also.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
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Add code to the generic pci_rom file to access the VGA ROM in PCI space
when needed.
Signed-off-by: Simon Glass <[email protected]>
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Each time U-Boot boots on Intel Crown Bay board, the displayed hard
drive information is wrong. It could be either wrong capacity or just
a 'Capacity: not available' message. After enabling the debug switch,
we can see the scsi inquiry command did not execute successfully.
However, doing a 'scsi scan' in the U-Boot shell does not expose
this issue.
SCSI: Target spinup took 0 ms.
SATA link 1 timeout.
AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8
Type: Hard Disk
Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512)
Found 1 device(s).
So uninitialized contents on the stack were passed to dev_print() to
display those wrong information.
The symptom were observed on two hard drives (one is Seagate, the
other one is Western Digital). The fix is to make sure the AHCI
interface is not busy by checking the error and status information
from task file register after enabling the port in ahci_port_start()
before proceeding other operations like scsi_scan().
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Now that we have a full VESA driver we may as well use that. We need to
support the VESA layer being set up by early start-up code or by
running a VGA ROM.
Signed-off-by: Simon Glass <[email protected]>
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Add a driver intended to cope with any VESA-compatible x86 graphics
adapter. It will not support ROMs which use OpenFirmware (Forth) since
there is no support for that in U-Boot. This means that MAC OS cards
will not work.
Signed-off-by: Simon Glass <[email protected]>
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These are quite common and we may as well press on and not be so picky.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Allow the supported modes to be listed when in debug mode.
Signed-off-by: Simon Glass <[email protected]>
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As it turns out this is a normal condition, so suppress the error.
Signed-off-by: Simon Glass <[email protected]>
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We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This code is too x86-dependent at present. Correct it so that it can run on
big-endian machines.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This stops the debug mode from working properly.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This board is still a non-generic board.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Cc: Andrea "llandre" Marson <[email protected]>
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It turns out that there are some panels where the pwm input is not active low,
so make it configurable.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
done they work like a regular LVDS panel.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
done they work like a regular LVDS panel.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
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Testing has shown that on sun4i the display backend engine does not have
deep enough fifo-s causing flickering / tearing in full-hd mode due to
fifo underruns. On sun4i use the display frontend engine to do the dma from
memory, as the frontend does have deep enough fifo-s.
As added advantage of this is that it results in much better memory bandwidth
as it reduces the amount of dram bank switches, for more details see:
http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html
Note that this changes the pipeline searched for in the simplefb node, we can
get away with doing this now, since no kernel has yet shipped with simplefb
dtb nodes, and I will make sure to get a simplefb node with the new pipeline
into 3.19 before it ships.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Instead of using the internal 'tx_clk' clock source, it is also
possible to use the pixel clock signal from the parallel LCD
interface ('pclk') as the reference clock for PLL.
The 'tx_clk' clock speed may be different on different boards/devices
(the allowed range is 8MHz - 30MHz). Which is not very convenient,
especially considering the need to know the exact 'tx_clk' clock
speed. This clock speed may be difficult to identify without having
device schematics and/or accurate documentation/sources every time.
Using 'pclk' is free from all these problems.
Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Convert GPIO names from Kconfig strings into pin numbers for
the 'ssd2828_config' struct. Add SSD2828 initialization between
enabling the parallel LCD interface and turning on the backlight.
Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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SSD2828 can take pixel data coming from a parallel LCD interface
and translate it on the fly into MIPI DSI interface for driving
a MIPI compatible TFT display. SSD2828 is configured over SPI
interface, which may or may not have MISO pin wired up on some
hardware. So a write-only SPI mode also has to be supported.
The SSD2828 support code is implemented as a utility function
and needs to be called from real display drivers, which are
responsible for driving parallel LCD hardware in front of the
video pipeline. The usage instructions are provided as comments
in the header file.
Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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And also add Kconfig option for selecting ELDO3 voltage. The reason
for having this option is that the Android kernel sets ELDO3 to
1.2V when powering up LCD in the case if 'lcd_if' configuration
variable is set to 6 (LCD_IF_EXT_DSI) in the FEX file. Most likely
to supply power for a SSD2828 chip.
However on the MSI Primo81 tablet, which is using this particular
'lcd_if = 6' setup for LCD, setting the ELDO3 voltage appears to
be unnecessary and it works regardless. Having no schematics of
this tablet, I can only guess that 1.2V is supplied to SSD2828
in some other way.
Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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We do not use the axp209 interrupt, and at least in my mini-x (which does not
have a power button) the pwr-button pin and the irq pin are soldered together,
so if the axp209 keeps it irq asserted too long it will see a 10s pwr-button
press and hard power off the board, disabling the irqs fixes this.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The clocks on the A80 are hooked up slightly different, add support for this.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Wait 1 second for the sdcard to respond, rather then waiting for
0xfffff milliseconds.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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phys_addr_t is designed for physical addresses that's why
use it.
Signed-off-by: Michal Simek <[email protected]>
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This patch fix the compilation warning
w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init':
w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects
argument of type 'unsigned int', but argument 4 has type 'phys_addr_t'
[-Wformat]
introduced by
"net: Declare physical address as phys_addr_t unsigned type"
(sha1: 16ae7827226ce8b255245d1932e8069f00997a26).
Reported-by: Tom Rini <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Use phys_addr_t for physical address declaration.
It is also unsigned type instead of sign.
Signed-off-by: Michal Simek <[email protected]>
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Show fpga_op->info even if desc->iface_fns is not defined.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Ensure that operations are correctly setup.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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SPL needs to detect FPGA device which will be used
for loading bitstream.
Signed-off-by: Michal Simek <[email protected]>
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Wider bus widths (larger than default 1 bit) appeared in MMC standard
version 4.0. So, for MMC cards of any earlier version trying to change
the bus width (including ext_csd comparison) does not make any sense.
It may work incorrectly and at least cause unnecessary timeouts.
So, just skip the entire bus width related activity for earlier versions.
Signed-off-by: Andrew Gabbasov <[email protected]>
Tested-by: Alexey Brodkin <[email protected]>
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If all the commands switching an MMC card to 4- or 8-bit bus width fail,
and the bus width for the controller and the driver is still set
to default 1 bit, there is no need to send one more command to switch
the card to 1-bit bus width. Also, if the card or host controller do not
support wider bus widths, there is no need to send a switch command at all.
However, if one of switch commands succeeds, but the subsequent ext_csd
fields comparison fails, the card should be switched to some other bus width
(next in the list for the loop), or to default 1-bit bus width as a last
resort. That's why it would be incorrect to just remove the 1-bit bus width
case from the list, it should still be processed in some cases.
panto: Minor cosmetic edit removing superfluous parentheses.
Signed-off-by: Andrew Gabbasov <[email protected]>
Tested-by: Alexey Brodkin <[email protected]>
Signed-off-by: Pantelis Antoniou <[email protected]>
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This extends the mmcinfo hardware partition info output to show
partitions with write reliability enabled with the "WRREL" string.
If the partition does not have write reliability enabled the "WRREL"
string is omitted; this is analogous to the ehhanced attribute.
Example output:
Device: OMAP SD/MMC
Manufacturer ID: fe
OEM: 14e
Name: MMC16
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.41
High Capacity: Yes
Capacity: 13.8 GiB
Bus Width: 4-bit
Erase Group Size: 8 MiB
HC WP Group Size: 16 MiB
User Capacity: 13.8 GiB ENH WRREL
User Enhanced Start: 0 Bytes
User Enhanced Size: 512 MiB
Boot Capacity: 16 MiB ENH
RPMB Capacity: 128 KiB ENH
GP1 Capacity: 64 MiB ENH WRREL
GP2 Capacity: 64 MiB ENH WRREL
Signed-off-by: Diego Santa Cruz <[email protected]>
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