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Prevent NULL pointer dereference with lockstep mode.
Since commit 21d03d60e909 ("j7200 defconfig: add rproc commands"),
issuing rproc init command with cluster configured in lockstep results
in a NULL pointer dereference.
This is because ti_sci_proc_request() is called on both cores on the
same cluster, without checking if they are populated.
To fix that, only request the core being probed, as there is no need to
request the other one.
Moreover, the old code was requesting both cores in lockstep mode, but
only releasing one:
it called k3_r5f_proc_request() with ti_sci_proc_release(), instead of
using k3_r5f_proc_request()/k3_r5f_proc_release() or
ti_sci_proc_request()/ti_sci_proc_release().
So, replacing k3_r5f_proc_request() by ti_sci_proc_request() restores
the intended behavior.
Fixes: 21d03d60e909 ("j7200 defconfig: add rproc commands")
Signed-off-by: Richard Genoud (TI) <[email protected]>
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U-Boot does not support modules, so having tristate options is useless.
Therefore this patch does a blind replace of all tristate options to
bool tree-wide.
Signed-off-by: Anshul Dalal <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Neha Malcom Francis <[email protected]>
Reviewed-by: Romain Gantois <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip
CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip/-/pipelines/597
- Add new rockchip custodian,
- Remove inactive rockchip custodian,
- Preemptively fix rk3528/rk356x DTS issue that will come with 7.1
upstream DTS sync,
- Fix typo in doc,
- Fix variable used before being set in rockchip_nfc,
- Fix asm-operand-widths clang warning for RK3528, RK3576 and RK3588,
- Work around HW undefined state for NVMEs on RK3588 Jaguar,
- Added support for new devices:
- LinkEase EasePi R1
- 9Tripod X3568 v4
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The oobfree[0].length calculation depends on the
rknand->metadata_size value, but this is calculated
after the function rk_nfc_ecc_init is called. Move this
calculation to a location before it's value is required.
Fixes: 1b3fcb3c0456 ("mtd: nand: raw: rockchip_nfc: add layout structure")
Signed-off-by: Johan Jonker <[email protected]>
Tested-by: Hüseyin BIYIK <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Quentin Schulz <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/hs/u-boot-i2c
i2c updates for 2026.10-rc1
- i2c: designware: fix i2c probe error
from Coben
It would be good to have some Testers...
- i2c: nx_i2c: updates from Peng
- Added License information
- use dev_read_addr_ptr()
- cmd: kconfig: i2c: add missing I2C API dependency
from Julien
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Mikhail Kshevetskiy <[email protected]> says:
This patch series add pin controller and gpio driver support for EN7523/
AN7581/AN7583 SoCs. The driver based on official linux airoha pinctrl
and gpio driver with Matheus Sampaio Queiroga changes.
The original Matheus Sampaio Queiroga driver can be taken from the repo:
https://sirherobrine23.com.br/airoha_en7523/kernel/src/branch/airoha_en7523_pinctrl
Additionally in the EN7523 case the patches removes existing gpio dts
nodes and replaces them with pinctrl node. It should not be very
dangerous, because:
* No official EN7523 gpio support present in U-Boot
* Legacy Linux EN7523 GPIO driver is mostly abandoned
* The same driver is planned for upstream linux/openwrt
This patchset includes bitfield.h patches created for Linux kernel by
Geert Uytterhoeven. It suits U-Boot fine. I preserve original author and
original commit messages. Please note me, if there is a better way.
The patches were tested on EN7523/AN7581/AN7583 boards.
Link: https://lore.kernel.org/r/[email protected]
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This patch adds U-Boot pin controller and gpio driver for Airoha EN7523 SoC.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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This patch adds U-Boot pin controller and gpio driver for Airoha AN7583 SoC.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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This patch adds U-Boot pin controller and gpio driver for Airoha AN7581 SoC.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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This patch introduce shared Airoha pinctrl code.
Also it sorts contents of pinctrl makefile.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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sorting rules:
* rules for generic pinctrl files placed first,
* obj-y rules,
* obj-$(CONFIG_ARCH_something) rules
* obj-$(CONFIG_PINCTRL_something) rules
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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Drop the driver-specific field_get() and field_prep() macros, in favor
of the globally available variants from <linux/bitfield.h>.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Drop the driver-specific field_get() and field_prep() macros, in favor
of the globally available variants from <linux/bitfield.h>.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Drop the driver-specific field_get() and field_prep() macros, in favor
of the globally available variants from <linux/bitfield.h>.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Drop the driver-specific field_get() and field_prep() macros, in favor
of the globally available variants from <linux/bitfield.h>.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Drop the driver-specific field_get() and field_prep() macros, in favor
of the globally available variants from <linux/bitfield.h>.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Prepare for the advent of globally available common field_get() and
field_prep() macros by undefining the symbols before defining local
variants. This prevents redefinition warnings from the C preprocessor
when introducing the common macros later.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Prepare for the advent of globally available common field_get() and
field_prep() macros by undefining the symbols before defining local
variants. This prevents redefinition warnings from the C preprocessor
when introducing the common macros later.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Prepare for the advent of globally available common field_get() and
field_prep() macros by undefining the symbols before defining local
variants. This prevents redefinition warnings from the C preprocessor
when introducing the common macros later.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Prepare for the advent of globally available common field_get() and
field_prep() macros by undefining the symbols before defining local
variants. This prevents redefinition warnings from the C preprocessor
when introducing the common macros later.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Prepare for the advent of globally available common field_get() and
field_prep() macros by undefining the symbols before defining local
variants. This prevents redefinition warnings from the C preprocessor
when introducing the common macros later.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Probing i2c slave device just needs its device address.
A certain type of chipsets such as RTC S35390A have no offset,
which means address length should be 0.
But the current designware_i2c_probe_chip function requires
offset 0 and its length 1.
This causes the designware-i2c to be initialized again and again.
Furthermore, after booting into kernel, the designware-i2c kernel
driver complains its controller timeout.
This patch fixes this misbehaviour in such way that only device
address is issued, no reinitialization needs when target device
not detected, the designware-i2c kernel driver continues working.
Signed-off-by: Coben Han <[email protected]>
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Add License information for nx_i2c driver.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Use dev_read_addr_ptr() which supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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zynqmp_mmio_read() and zynqmp_mmio_write() selected between direct MMIO
and the firmware (PM_MMIO_READ/WRITE) interface with an in-function
IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) / current_el() check. Generic arch
code should not carry firmware-specific ifdefs, and with SCMI the access
method changes again.
Split the accessors like the multiboot and bootmode hooks: the weak
default in arch/arm/mach-zynqmp does the direct MMIO access (used in SPL,
at EL3 and when no firmware is present), while firmware-zynqmp.c provides
a strong definition that issues the firmware call and falls back to the
direct access in SPL/EL3 where the SMC path is unavailable. The raw MMIO
primitives zynqmp_mmio_rawread() and zynqmp_mmio_rawwrite() are exported
for the shared fallback, and the read-modify-write helper now uses the
raw read instead of routing through the firmware-aware accessor.
The firmware-vs-MMIO decision is selected at link time, so adding SCMI
later only requires a third strong definition with no changes to generic
code.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/d532df144d2c8e34be835bad6d0de3b26befdf01.1782219202.git.michal.simek@amd.com
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versal_net_get_bootmode() open-coded the
IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) selection between the firmware call
zynqmp_pm_get_bootmode_reg() and a direct readl() in board code. Like
the Versal change, move the whole function behind an overridable hook so
generic board code stays free of firmware specifics and is ready for
SCMI.
The weak versal_net_get_bootmode() in arch/arm/mach-versal-net does the
plain MMIO read via versal_net_bootmode_reg() and decodes it (used at EL3
and without firmware). When CONFIG_ZYNQMP_FIRMWARE is enabled,
firmware-zynqmp.c provides a strong definition that reads the register
through the firmware call, falling back to the direct read at EL3 where
the SMC path to firmware is unavailable. This preserves the existing
firmware-based bootmode behaviour while removing the firmware interface
from board code; the now unused zynqmp_firmware.h include is dropped.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/be67e9c6d0bc36840a46594413886d2003967c64.1782219202.git.michal.simek@amd.com
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versal_get_bootmode() lived in board code and open-coded the
IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) selection between the firmware call
zynqmp_pm_get_bootmode_reg() and a direct readl(). To keep generic board
code free of firmware specifics and SoC register details and ready for
SCMI, move the whole function, including the alt-shift and mask decoding,
behind an overridable hook.
The weak versal_get_bootmode() in arch/arm/mach-versal does the plain
MMIO read via versal_bootmode_reg() and decodes it (used at EL3 and
without firmware). When CONFIG_ZYNQMP_FIRMWARE is enabled,
firmware-zynqmp.c provides a strong definition that reads the register
through the firmware call, falling back to the direct read at EL3 where
the SMC path to firmware is unavailable. This preserves the existing
firmware-based bootmode behaviour while removing the firmware interface
from board code; the now unused zynqmp_firmware.h include is dropped.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/d60073feed8da8d3aff9eabee6ab132e0bbd0f8e.1782219202.git.michal.simek@amd.com
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versal_multi_boot() in board code selected between the firmware call
zynqmp_pm_get_pmc_multi_boot_reg() and a direct readl() based on an
IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) check. Generic board code should not
carry firmware-specific ifdefs, and this becomes harder to maintain once
SCMI introduces yet another access method.
Introduce an overridable accessor versal_pmc_multi_boot(). The weak
default lives in arch/arm/mach-versal and performs the plain MMIO read
(used at EL3 and when no firmware is present). When CONFIG_ZYNQMP_FIRMWARE
is enabled, firmware-zynqmp.c provides a strong definition that issues the
firmware call, falling back to the direct read at EL3 where the SMC path
to firmware is unavailable. The shared MMIO read is factored into
versal_multi_boot_reg() so the firmware override does not duplicate it.
versal_multi_boot() keeps the generic JTAG/QEMU workaround and simply
calls the accessor, so board code no longer references the firmware
interface for the multiboot register. The firmware-vs-MMIO decision is
selected at link time, and adding SCMI later only requires a third strong
definition with no board-code changes.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/199ef6a1411c54f154fe4a43b5fef166b9927f7a.1782219202.git.michal.simek@amd.com
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versal2_multi_boot() in board code selected between the firmware call
zynqmp_pm_get_pmc_multi_boot_reg() and a direct readl() based on an
IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) check. Generic board code should not
carry firmware-specific ifdefs, and this becomes harder to maintain once
SCMI introduces yet another access method.
Introduce an overridable accessor versal2_pmc_multi_boot(). The weak
default lives in arch/arm/mach-versal2 and performs the plain MMIO read
(used at EL3 and when no firmware is present). When CONFIG_ZYNQMP_FIRMWARE
is enabled, firmware-zynqmp.c provides a strong definition that issues the
firmware call, falling back to the direct read at EL3 where the SMC path
to firmware is unavailable. The shared MMIO read is factored into
versal2_multi_boot_reg() so the firmware override does not duplicate it.
versal2_multi_boot() keeps the generic JTAG/QEMU workaround and simply
calls the accessor, so board code no longer references the firmware
interface and the now unused zynqmp_firmware.h include is dropped. The
firmware-vs-MMIO decision is selected at link time, and adding SCMI later
only requires a third strong definition with no board-code changes.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/0033a1fa8efb4ae0c3ac6a6f5c5c1b4e0f22f02c.1782219202.git.michal.simek@amd.com
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The XCZU3TCG device shares IDCODE 0x04718093 with XCZU3TEG but has
the GPU disable eFuse bit set (Consumer Grade, no GPU). Previously,
the TEG detection branch appended "teg" unconditionally, causing
U-Boot to report the device as zu3teg and failing bitstream ID
checks for xczu3tcg bitstreams.
Check EFUSE_GPU_DIS_MASK in the TEG branch to distinguish the two
sub-variants, mirroring the existing EG/CG detection logic:
- GPU disabled -> TCG family -> "zu3tcg"
- GPU enabled -> TEG family -> "zu3teg"
Fixes: fa2f0c97af96 ("soc: zynqmp: Add the IDcode for TEG variant")
Signed-off-by: Padmarao Begari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/[email protected]
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Agilex/Stratix10
Replace the conditional compilation checks for
CONFIG_ARCH_SOCFPGA_AGILEX and CONFIG_ARCH_SOCFPGA_STRATIX10 with
CONFIG_FPGA_INTEL_SDM_MAILBOX.
Signed-off-by: Danish Ahmad Rosdi <[email protected]>
Signed-off-by: Chen Huei Lok <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add missing .priv_auto field to the driver. Without it,
struct ufs_versal2_priv is never properly allocated and dev_get_priv()
returns NULL, leading to DDR corruption at low DDR addresses.
Fixes: b5ac5f030720 ("ufs: ufs-amd-versal2: Add support for AMD UFS controller")
Signed-off-by: Pranav Tilak <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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This reverts commit b42c67188c14 ("mmc: sdhci-cadence: trigger tuning
for SD HS mode on SD6HC (v6) PHY").
The reverted patch introduced several issues:
1. Non-standard tuning trigger: The SD Physical Layer Specification
only mandates execute_tuning for SDR50 and SDR104 UHS-I modes.
Triggering tuning for SD High Speed mode is outside the spec and
is handled via a non-standard set_ios_post callback rather than
through the established SDHCI framework tuning path.
2. Non-standard device tree property: The patch introduced a new
"cdns,sd-hs-tuning" DT property to opt into SD HS tuning. This
is not aligned with existing DT bindings and bypasses the standard
MMC capability negotiation mechanism.
3. Incorrect tunable mode allowlist: The sdhci_cdns6_mode_is_tuned()
function includes SD_HS, UHS_SDR50, and MMC_HS_400_ES as tunable
modes. According to the Cadence SD6HC IP User Guide (section 7.5.2,
Figure 18), tuning is only required for UHS-I SDR104 (SD) and
HS200 (eMMC). SD High Speed, UHS-I SDR50, and DDR50 only require
a PHY settings update from the pre-calculation script, not the
tuning procedure. HS400 transitions through HS200 and reuses its
tuned DLL value with a partial settings update. HS400ES only
requires a plain settings update from the calculation script with
no dependency on HS200 tuning.
4. Tuned state management outside the framework: The patch manually
tracks tuned DLL state (tuned_mode, tuned_dll_slave_ctrl) and
restores it across PHY reconfigurations. This duplicates
responsibility that belongs in the core MMC tuning framework and
adds unnecessary complexity to the driver.
Reverting to realign the driver with the IP documentation and the SD
Physical Layer Specification.
Signed-off-by: Tanmay Kathpalia <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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When a UHS card successfully negotiates 1.8V signaling during normal
initialization, the host voltage switch is performed as part of the
ACMD41 handshake. Without this fix, the warm-reboot recovery path
would fire again immediately after, switching the host voltage a
second time unnecessarily.
Add a check so the recovery path is only entered when the voltage
switch was not already performed during the current initialization
session.
Fixes: 906ee6785b1c ("mmc: sd: Handle UHS-I voltage signaling without power cycle")
Signed-off-by: Tanmay Kathpalia <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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When one power domain fails to get attribute, continue getting attribute
for remaining power domains, not return probe failure. So other power
domains are still functional.
It is possible that one power domain is assigned to other agent or this
power domain is disabled by HW fuse, so platform returns denied or other
error.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Make CAAM_64BIT selectable only in case FSL_CAAM is selected,
otherwise CAAM_64BIT shows up in configs of unrelated platforms.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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mpc8xxx_gpio_open_drain_on() / _off() helpers can program GPODR
(open-drain enable) on QorIQ silicon, but they are not called.
The open-drain capability is therefore unreachable from the GPIO uclass.
Adding a set_flags op for the GPIOD_OPEN_DRAIN, plus a get_flags for the
reports of state by reading GPDIR and GPODR back.
For existing callers, it is unchanged: direction_input,
direction_output, get_value, set_value and get_function still drive
the same registers as before. The new ops only become observable when
a caller explicitly asks for the GPIOD_OPEN_DRAIN flag (or queries
flags via the uclass).
Signed-off-by: Vincent Jardin <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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This reverts:
- commit e49c84f7bb7b ("doc: usage: cmd: reset: specify when the -edl
option is available")
- commit 1076feb8a3f9 ("cmd: boot: fix edl being shown when not
supported")
- commit 63c806ba0e12 ("qcom_defconfig: enable psci based sysreset")
- commit ef06c5d76ff4 ("cmd: boot: Add '-edl' option to reset command
documentation")
- commit 32825eaddc37 ("sysreset: Implement PSCI based reset to EDL mode
for QCOM SoCs")
- commit fcb48b89813b ("drivers: sysreset: Add sysreset op that can take
arguments")
There was a conflict reverting commit 63c806ba0e12 ("qcom_defconfig:
enable psci based sysreset") due to commit 02ef1859b44f ("configs:
Resync with savedefconfig"), but the conflict resolution was trivial.
The args support for the sysreset uclass contains a logic bug. The first
sysreset device implementing the request_arg callback will consume the
args, not support the specified arg and thus return -EPROTONOSUPPORT
which will stop the iteration over all sysreset devices.
This is an issue if one has multiple sysreset devices and each with
support for different (valid) args. If a sysreset device implements a
-dummy argument and another -foo and a user calls reset -dummy from the
U-Boot CLI, it'll depend on which sysreset device will be attempted
first. If it is the one implementing -foo, it'll return it doesn't
support the argument with -EPROTONOSUPPORT in which case the device
implementing -dummy will never be attempted and instead we'll do a cold
reset which is very likely not what's expected from the user.
Casey suggested[1] we revert this and start from scratch again with a
different implementation instead.
[1] https://lore.kernel.org/u-boot/[email protected]/
Acked-by: Casey Connolly <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
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Add bootdev_hunt_fallthrough() test to verify that 'bootflow scan -l'
falls back to a lower-priority bootdev when a higher-priority hunter
fails.
Introduce a simple 'sandbox-bootdev' device for the test. The new
bootdev can be configured to produce an error at the hunting stage.
Introduce new host_set_flags_by_label() API and a flags field to
'host_sb_plat' to simulate a bootdev hunter failure for the test.
Adjust boot{dev,flow} tests which depend on bootdev hunters.
Signed-off-by: Denis Mukhin <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with
the same read path flags.
SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's
status register layout: the GD55LB02GF uses a 5-bit block protect
field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet
"Status Register Block Protection").
The generic stm-lock helpers drive only BP0..BP2 and assume SR1
bit 5 is TB, but on this part SR1 bit 5 is BP3.
Enabling either flag would leave BP3..BP4 unmanaged or corrupt
BP3 on every lock op.
A proper support needs a vendor specific lock callback, it is out
of scope for this table update.
Signed-off-by: Vincent Jardin <[email protected]>
Suggested-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Takahiro Kuwano <[email protected]>
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Convert the Layerscape PCIe endpoint driver to use device and ofnode-based
APIs instead of legacy FDT interfaces.
Replace devfdt_get_addr_index_ptr(), fdt_get_named_resource(),
fdtdec_get_bool(), and fdtdec_get_int() with their modern counterparts such
as dev_read_addr_index_ptr(), dev_read_resource_byname(),
dev_read_bool(), and dev_read_s32_default().
Also remove the dependency on gd->fdt_blob and global data access.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Use dev_read_addr_index_ptr() which support both live device tree and flat
DT backends, avoiding direct dependency on devfdt_* helpers.
No functional changes
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Use dev_read_addr_x APIs which support both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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devfdt_get_addr_ptr() + map_physmem() could be simplifed with
devfdt_remap_addr(). But to avoid direct dependency on devfdt_* helpers,
use dev_remap_addr().
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Use dev_read_addr_index() which supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.
While at here, correct the return value check.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-next-20260629:
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/30562
Fastboot:
- Add support for CMD_FASTBOOT_ABORT_KEYED
- Enable CMD_FASTBOOT_ABORT_KEYED for qualcomm phones
USB Gadget:
- f_mass_storage: Disable eps during disconnect
- f_sdp: Fix spl load failure error handling
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With a recent change to the UFS driver, now all clocks need to be
available. Add all the clocks from the TCSRCC block on Milos.
Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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With a recent change to the UFS driver, now all clocks need to be
available. Add them.
Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Ryan Chen <[email protected]> says:
AST2700 is the 8th generation of Integrated Remote Management
Processor introduced by ASPEED Technology Inc. It is a Board
Management Controller (BMC) SoC family with a dual-die architecture:
SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and
SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs,
clock dividers and reset domains.
Link: https://lore.kernel.org/r/[email protected]
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