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The inclusion of the drivers was wrapped by an “if not SPL/TPL”, which
always excluded them from SPL/TPL build.
Signed-off-by: Jörg Sommer <[email protected]>
Fixes: 591257b05cab ("rng: Introduce SPL_DM_RNG")
Reviewed-by: Tom Rini <[email protected]>
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Change "Angelo Dureghello" emails replacing non-existing domain with the
currently working one.
Signed-off-by: Angelo Dureghello <[email protected]>
Acked-by: Michal Simek <[email protected]>
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part_get_info_ubi() passes the UBI volume name straight to snprintf() as
its format argument:
snprintf(info->name, PART_NAME_LEN, vol->name);
A volume name that contains a '%' is then interpreted as a printf
conversion specifier, yielding a wrong partition name or reading
unintended variadic arguments; a '%n' would be undefined behaviour.
Volume names are user-defined and boot methods select images by volume
name, so copy the name through a "%s" format instead.
Fixes: aa5b67ce2262 ("disk: support UBI partitions")
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Use device managed GPIO and reset get to automatically free
those resources up. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Avoid repeated link attempts for these controllers. In case the
controller link is up, this is a noop since the probe() already
finished. In case the controller link is down, a repeated link
up attempt seems to require reset of both PCIe controllers, which
is not desired. It is also unlikely that a repeated link attempt
would bring the link up, as U-Boot does not support hotplug anyway.
Therefore, prevent repeated link attempts.
Signed-off-by: Marek Vasut <[email protected]>
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Use generic request_firmware_into_buf_via_script() instead of local
implementation of similar functionality. This reduces code duplication.
Signed-off-by: Marek Vasut <[email protected]>
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Currently the driver can not report core status. Determine SCP core
state via SCP_CPUWAIT_WAIT bit and use SCMI PD protocol POWER_STATE_GET
call to determine CR52 and CA720AE core state. Report the core states.
Signed-off-by: Marek Vasut <[email protected]>
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Currently the driver could only start cores. Add support for stopping
CR52 and CA720AE cores via SCMI. Note that the SCP core is controlled
via direct register IO.
Signed-off-by: Marek Vasut <[email protected]>
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Use SCP core init code, which resets the SCP core, as a SCP core stop.
Once stop is invoked, the SCP core is reset and ready to be loaded with
new software, which is practical for SCP firmware development.
Signed-off-by: Marek Vasut <[email protected]>
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Move the SCP initialization from board file into remoteproc driver
where this is supposed to be. Add SCP MDLC DT node and describe the
SCP reset controlled by the SCP MDLC in remoteproc DT node. Adjust
the driver to control the SCP reset via reset framework instead of
the current board-specific register poking.
Signed-off-by: Marek Vasut <[email protected]>
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In case of SCMI protocol error, print SCMI domain number and error
code both as hexadecimal and decimal to make it easier to interpret
the error.
Signed-off-by: Marek Vasut <[email protected]>
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Clear the transport flags field before starting new transfer.
The current SDK SCP is not affected by this in any way, but it
is better to clear the field to be correct.
Signed-off-by: Marek Vasut <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-net
Pull request net-20260813.
net:
- phy: dp83867: enable extended read / write for driver
- phy: fix duplicate eth_phy binding
- Drop unnecessary device_set_name
- dwc_eth_xgmac: Return -ENODEV when phy_connect() fails
- nfs: clean up bounds checks in nfs_readlink_reply()
- rtl8169: add support for RTL8126A and RTL8127A
- srand_mac(): fix -ENODEV crash with CONFIG_DM_RNG
net-legacy:
- Fix out-of-bounds write in IP fragment reassembly
- test: net: add regression test for IP reassembly overflow
net-lwip:
- Add tftpsrv command
- Handle chained pbufs in transmit path
- sntp: fix netif leak when ntpserverip is unset
- wget: free mbedtls x509 cert context to avoid memory leak
- Fix DHCP fine timer interval
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There are EEMI firmware hooks available but they are also IO versions of it
that's why remove ZYNQMP_FIRMWARE depency from UFS driver.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/85cbacdc7492890c76396974d24fff607c2088ad.1785394153.git.michal.simek@amd.com
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The M-PHY and SRAM readiness poll loops move out of the UFS controller
driver and into the firmware backend, exposed as blocking waits with
a caller-owned timeout budget. This keeps the UFS driver backend-agnostic
and lets an other backends offload the wait to the platform in a single
call instead of round-tripping every poll.
set_sram_bypass() now performs the SRAM_CSR read-modify-write in the
firmware layer.
Hook up functions are also update to reflect their usage.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/26bc9aa2c02921690e126ab3401f7974ef04ad6e.1785394153.git.michal.simek@amd.com
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Move the controller/PHY reset and SRAM-bypass sequence from
hce_enable_notify(PRE_CHANGE) into ufs_versal2_init().
The reset sequence releases the host controller from reset, and the UFS
core reads the capability and version registers right after .init() and
before ufshcd_hba_enable() (the only caller of hce_enable_notify()).
Doing the reset in .init() ensures those registers are read after the
controller is out of reset, and keeps the driver aligned with Linux.
ufs_versal2_phy_init() stays in POST_CHANGE.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/6b4cbfa6cc58bef86da86971e4b27726a4e510f0.1785394153.git.michal.simek@amd.com
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Add firmware interface for UFS access but also keep IO interface when
firmware is not enabled.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/6419fe4f6f1f451aee624c7762b7aa690d50e498.1784870711.git.michal.simek@amd.com
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asm/arch/sys_proto.h is included twice that's why remove one.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/cd3c11a7e09ed8db3945910cdfed0eb860dcd61e.1784870326.git.michal.simek@amd.com
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Starting the GENFIFO after each CMD and ADDR entry creates a gap
between the address phase (TX) and data phase (RX). For read commands
without dummy cycles, the controller is still driving DQ2/DQ3 HIGH
when the flash switches to output mode, causing a bus conflict.
Split the GENFIFO helper into a write-only variant and a
start-and-wait variant. Queue CMD, ADDR and dummy entries without
starting the GENFIFO. The data phase appends its entry and starts
the queued sequence, keeping the address-to-data transition
continuous.
Since genfifo_cmd() no longer triggers after each entry, operations
without a data phase have no trigger path. Call start_gen_fifo()
from exec_op() before deasserting chip select to execute the queued
CMD and ADDR entries.
Fixes: 22cca1730ec4 ("spi: zynqmp_gqspi: Add support for ZynqMP qspi driver")
Signed-off-by: Suraj Kakade <[email protected]>
Signed-off-by: Padmarao Begari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/[email protected]
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We can have many pci hotplug groups, each introduced
by a "pci@<addr>" token such as,
pci_iommu_extra=pci@0x3600000,1.0.0,hp,pci@0x3700000,1.0.0,hp,
pci@0x3800000,1.0.0,hp,pci@0x3900000,1.0.0,hp
Without this fix, we have the error:
Added iommu map for hotplug 1.0.0
ERROR: invalid action in extra iommu entry
ERROR: invalid action in extra iommu entry
ERROR: invalid action in extra iommu entry
Fixes: 2a5bbb13cc39 ("pci: layerscape: add a way of specifying additional iommu mappings")
Signed-off-by: Vincent Jardin <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The TPS65219 bind function continues when the regulators subnode is
missing. This causes pmic_bind_children() to be called with an invalid
ofnode and permits a misleading message indicating that the subnode
was found.
Return -ENXIO when the regulators subnode is absent, matching the
behavior of other TI PMIC drivers.
Signed-off-by: Kumara Bhimeswararao Matsa <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Preparing to add the AMD/Xilinx SCMI vendor protocol driver, support probe
of SCMI vendor ID 0x81. Add the protocol ID, the per-agent protocol device
slot, the probe/lookup switch cases and the scmi command name, gated by a
Kconfig option for conditional compilation.
The same wiring has been done by commit 7830ccc77a13 ("firmware: scmi:
Support probe vendor ID 0x80 and 0x82").
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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U-Boot running as a coreboot payload obtains serial console
information either from the coreboot table or from the ACPI DBG2
table.
When serial console support is disabled in coreboot, the coreboot
table does not contain serial information. In this case U-Boot falls
back to parsing the DBG2 table.
Some AMD platforms or any other platforms that uses memory-mapped I/O
advertise the debug UART using DBG2 subtype 0x0012 ("16550-compatible
with parameters defined in Generic Address Structure"). U-Boot
currently accepts only subtype 0x0000, causing DBG2 UART detection to
fail and leaving no console output.
Accept subtype 0x0012 as well and keep the existing handling logic.
Signed-off-by: Desapogu Jayaramudu <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Simplify the code, replace env_get_f() with env_get_yesno(). The
env_get_yesno() internally calls env_get() which may fall back to
env_get_f() if the environment access is not initialized yet.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-usb
- MTU3 DT bindings alignment with Linux DT bindings.
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MediaTek platforms may need the MTU3 controller before U-Boot proper is
available, but the driver is currently selected and built only with the
main U-Boot configuration symbols.
Add an explicit SPL controller option with host and gadget modes. Make
the driver build and its role checks phase-aware so each phase can select
the MTU3 role it needs without coupling it to the U-Boot proper controller
configuration.
The upstream binding locates the xHCI child registers through the parent
ranges property. Select SPL_OF_TRANSLATE for host mode so SPL can resolve
that address before mapping it.
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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The MTU3 glue driver expects a synthetic mediatek,ssusb child that
combines the device and xHCI register windows. Upstream devicetrees
instead put the device resources on the controller node and describe the
xHCI window with a standard child node, so U-Boot cannot use an upstream
topology.
Switch to the upstream layout. The controller owns the shared resources
and the device MAC, with the device register offsets relative to it as in
Linux. The gadget role binds as a node-less internal device, while the
host role binds to an enabled xHCI child and uses its own clocks,
supplies and register window. dr_mode selects the role and defaults to
otg, and the Kconfig choice constrains which role the build provides.
The legacy child layout is rejected explicitly so its combined register
window cannot be mistaken for the device MAC.
Convert the in-tree MT8183 and MT8512 devicetrees in the same commit so
neither platform is left without USB. MT8512 stays peripheral-only
because its xHCI host interrupt is not documented and the
mediatek,mtk-xhci binding requires it.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
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Switch from FASTAUTO to FAST mode and lane 2 to achieve
higher throughput. Drop the 64bit address quirk.
Signed-off-by: Tuyen Dang <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Add device tree compatible string "renesas,rcar-gen5-rpc-if" to
the driver to match on upstream RPC DT node in R-Car Gen5 DTs.
Signed-off-by: Marek Vasut <[email protected]>
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Remove the IF from RPCIF to align the register macros with each other.
No functional change.
Fixes: d5162463243d ("mtd: spi: renesas: Configure RPC PHY timing registers")
Signed-off-by: Marek Vasut <[email protected]>
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Add device tree compatible string "renesas,rcar-gen5-rpc-if" to
the driver to match on upstream RPC DT node in R-Car Gen5 DTs.
Adjust Kconfig to allow driver enablement on all 64bit R-Car.
Signed-off-by: Marek Vasut <[email protected]>
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Simplify the DT register address parsing using dev_read_addr_name(),
switch away from raw fdt_*() functions. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek
* Clock fix for MT8188 (Genio 700/520)
* SPL support preparatory patch for MT8188.
* Compile error fix for when enabling LWIP network stack on some MediaTek targets.
* Fix a regression in clock driver binding from the previous PR.
* Add display-related clocks on MT8188.
* Another wave of clock driver refactoring and de-duplication.
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https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv
CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv/-/pipelines/884
- board: MPFS: add hardware RNG support and fix RNG consumers
- board: sophgo: add support for Milk-V Duo 256M
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https://git.u-boot-project.org/u-boot/custodians/u-boot-watchdog
CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-watchdog/-/pipelines/867
u-boot-watchdog changes 2026-08-03:
- cyclic: get rid of cyclic_get_list() helper (Rasmus)
- cyclic: return early from cyclic_run() if the list is empty (Rasmus)
- watchdog: ast2600: add AST2700 support (Ryan)
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https://git.u-boot-project.org/u-boot/custodians/u-boot-sh
- R-Car Gen3 clean ups and size optimization.
- R-Car Gen4 proper PCIe clock generator driver.
- R-Car Gen5 support for newer SCP firmware version.
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Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
the clock is currently disabling them.
Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
active-high semantics.
Signed-off-by: Julien Stephan <[email protected]>
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Link: https://patch.msgid.link/20260728-mt8188-clk-fix-top0-gate-polarity-v1-1-56bc92ba6055@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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The MPFS mailbox driver currently checks the BUSY bit at the start of
mpfs_mbox_send() and immediately returns -EBUSY if the controller is
busy.
On MPFS, BUSY may be transiently asserted during early boot even though
no other U-Boot service is actively executing. In Linux, returning
-EBUSY here is retryable via the mailbox framework and scheduler, but in
U-Boot this results in a hard failure.
Replace the immediate BUSY check with a bounded wait using
regmap_read_poll_timeout(), waiting for the controller to become idle
before issuing a new request. This preserves the intent of the BUSY
check while avoiding spurious early-boot failures in U-Boot’s
synchronous, polled execution model.
The timeout is conservative and based on observed MPFS behaviour, where
BUSY clears within a few milliseconds.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
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The MPFS mailbox driver used unbounded polling loops and treated the
BUSY bit as a fatal condition in several paths. On MPFS, BUSY may be
transiently reasserted even after response data is written, which is
observable in U-Boot’s synchronous, polled execution model.
Replace the unbounded loops with a bounded
regmap_read_poll_timeout()-based helper that waits for the controller to
become idle.
This preserves existing behaviour while preventing infinite stalls
and avoiding spurious failures during early boot.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
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Add a U-Boot RNG driver for Microchip's PolarFire SoC (MPFS). The
hardware RNG is accessed indirectly via the MPFS system controller using
the mailbox interface.
The driver implements the UCLASS_RNG interface, requesting random data
from the system controller and returning it to the caller.
This allows use of the PolarFire SoC hardware RNG via the
standard 'rng' command and DM RNG API.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The MPFS RNG driver is not described by the device tree and is instead
registered dynamically by the system controller. Explicitly bind the
MPFS RNG driver as a child device during system controller probe.
This ensures the RNG device is instantiated and available via UCLASS_RNG
without requiring a device tree node.
Signed-off-by: Jamie Gibbons <[email protected]>
Acked-by: Conor Dooley <[email protected]>
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The MPFS system controller run_service() helper only submits the mailbox
request but does not read back the response data. However, the caller
must explicitly receive the response.
Add a public system controller helper to receive mailbox service
responses to populate the response buffer after issuing a system
controller request.
Without this, the drivers copy uninitialised stack data instead of
mailbox response data, resulting in deterministic output.
Signed-off-by: Jamie Gibbons <[email protected]>
Acked-by: Conor Dooley <[email protected]>
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RTL8126A and RTL8127A share most of the register layouts and quirks with
RTL8125 series, but require explicit desc type and CRC-drop setup during
init.
This patch adds PCI IDs and MAC versions. RTL8126A is 0x66 and RTL8127A
is 0x6e. And RTL8127A requires Tx Desc V3 format and an additional RADM
FIFO protection configuration according to vendor driver.
Signed-off-by: Javen Xu <[email protected]>
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The AST2700 reuses the AST2600 watchdog block unchanged. Bind the
driver to the aspeed,ast2700-wdt compatible and enable WDT_AST2600
on the AST2700.
Signed-off-by: Ryan Chen <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Reduce the PFC tables further by gating DRIF, MLB, TMU, TPU and SATA
behind PINCTRL_PFC_FULL, none of which are currently supported by
U-Boot. This helps reduce the size of the bootloader in 4 kiB range.
Signed-off-by: Marek Vasut <[email protected]>
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Reduce the PFC tables further by gating DRIF, MLB, TMU and TPU
behind PINCTRL_PFC_FULL, none of which are currently supported by
U-Boot. This helps reduce the size of the bootloader in 4 kiB range.
Signed-off-by: Marek Vasut <[email protected]>
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Reduce the PFC tables further by gating DRIF, MLB, TMU, TPU and SATA
behind PINCTRL_PFC_FULL, none of which are currently supported by
U-Boot. This helps reduce the size of the bootloader in 4 kiB range.
Signed-off-by: Marek Vasut <[email protected]>
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The clock controller driver for the device which supplies reference
clock to the PCIe core and bus may not implement .enable / .disable
callbacks in case the clock supplied by the device are always on,
in which case the clk_prepare_enable() call returns -ENOSYS. This
is the case on e.g. 9FGV0441. Handle the -ENOSYS as a valid return
value and proceed with probing.
Signed-off-by: Marek Vasut <[email protected]>
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Add driver for Renesas 9-series PCIe clock generators. This driver
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators.
The driver is capable of configuring per-chip spread spectrum mode
and output amplitude, as well as per-output slew rate.
Losely based on Linux 7.1 commit
5ec820fc28d0 ("clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841")
Signed-off-by: Marek Vasut <[email protected]>
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driver
The SCMI IDs did not change between SDK SCP 4.32 and SDK SCP 4.36.
Add SDK SCP 4.36 as supported version and reuse SDK SCP 4.32 remap
table.
Signed-off-by: Marek Vasut <[email protected]>
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