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Make SPL_RAM_SUPPORT a hidden Kconfig symbol, automatically selected
by SPL_RAM_DEVICE or SPL_DFU. Avoids the situation where SPL_RAM_SUPPORT
may be enabled without the other two being enabled, which results in the
following build warning:
common/spl/spl_ram.c:19:14: warning: ‘spl_ram_load_read’ defined but not used [-Wunused-function]
19 | static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
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Signed-off-by: Jerome Forissier <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx changes for v2025.01-rc1
kbuild:
- Add rules for automatically applying DT overlays
Microblaze:
- Enable bootscript location via DT
AMD/Xilinx
- Enable SIMPLE_PM_BUS by default
ZynqMP:
- DT updates and alignments with dt-schema
- Call fdtoverlay via make directly
- Enable non-invasive CCI-400 PMU debug
- Disable secure access for boot devices
- Add new zynqmp reboot command
Versal NET:
- Cleanup spi_get_env_dev()
Kria:
- Add bootmenu support
sdhci:
- Do not call device_is_compatible everywhere
net:
- Remove is-internal-pcspma DT flag
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In case the cyclic framework is enabled, poll the card detect of already
initialized cards and deinitialize them in case they are removed. Since
the card initialization is a longer process and card initialization is
done on first access to an uninitialized card anyway, avoid initializing
newly detected uninitialized cards in the cyclic callback.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.
Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
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There are lot of device_is_compatible() present in the driver.
Remove them and replace with a variables "SDHCI_COMPATIBLE_SDHCI_89A"
and "SDHCI_COMPATIBLE_VERSAL_NET_EMMC" with match data.
This change saves the space and reduce the execution time.
Signed-off-by: Padmarao Begari <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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This patch fixes timeout issues seen on large NOR flash.
For full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7)
opcode. Use a different timeout for full-chip erase than for other
commands.
[Ported from Linux kernel commit
09b6a377687b ("mtd: spi-nor: scale up timeout for
full-chip erase") ]
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
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Add support for iMX93 low performance parts 9302 and 9301 which
restrict to low drive voltage only.
The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU
and A55 core1 (9301) disabled.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Simon Glass <[email protected]> says:
This series includes the patches needed to make make the EFI 'boot' test
work. That test has now been split off into a separate series along with
the EFI patches.
This series fixes these problems:
- sandbox memory-mapping conflict with PCI
- the fix for that causes the mbr test to crash as it sets up pointers
instead of addresses for its 'mmc' commands
- the mmc and read commands which cast addresses to pointers
- a tricky bug to do with USB keyboard and stdio
- a few other minor things
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The driver model deadline for USB was in 2019, so drop the old USB
keyboard code, to avoid needing to deal with the extra code path.
Drop the unnecessary #ifdef around USB_KBD_BOOT_REPORT_SIZE while we
are here.
Signed-off-by: Simon Glass <[email protected]>
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Devices should be probed when they are used, not before. Drop this
boot-time probing.
Signed-off-by: Simon Glass <[email protected]>
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We should not need to announce this device. Drop the message.
Signed-off-by: Simon Glass <[email protected]>
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Jim Liu <[email protected]> says:
Modify npcm8xx new boot design.
Correct memory setting and set gpio default value.
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Clear all gpio events to avoid unexpected interrupts
during kernel booting.
Signed-off-by: Stanley Chu <[email protected]>
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Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which
export a SHA accelerator interface for SoC to use.
Note that CPTRA 1.0 supports only SHA384 and SHA512 and this
patch is verified by the 'hash test sha384/sha512' commands.
Signed-off-by: Chia-Wei Wang <[email protected]>
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Prepare v2024.10-rc5
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https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request efi-next-20241024
UEFI:
* Use generated UUIDs in UEFI capsules:
- efi: define struct efi_guid
- lib: uuid: add UUID v5 support
- efi: add a helper to generate dynamic UUIDs
- doc: uefi: document dynamic UUID generation
- sandbox: switch to dynamic UUIDs
- lib: uuid: supporting building as part of host tools
- include: export uuid.h
- tools: mkeficapsule: use u-boot UUID library
- tools: mkeficapsule: support generating dynamic GUIDs
- test: lib/uuid: add unit tests for dynamic UUIDs
- test: lib/uuid: add tests for UUID version/variant bits
* Minor code clean-up
- shorten efi_bootmgr_release_uridp_resource()
- rename efi_bootmgr_image_return_notify
- return the correct error in efi_bootmgr_release_uridp()
- Kconfig: clean up the efi configuration status
- Use puts() in cout so that console recording works
- Put back copyright message in helloworld.c
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The current documentation for the bootcount API is on our website and
not the old wiki, update the link in two places.
Signed-off-by: Tom Rini <[email protected]>
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Move this header to include/u-boot/ so that it can be used by external
tools.
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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into next
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22315
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- Aspeed: Add AST2700 board (Ibex RISC-V core) support
- Add timer, dram controller, network support
- Sophgo: Add clock controller support for Milk-V Duo
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Changing the duty-cycle should not blindly override (and clear) the
enable (EN) bit if it has already been set. For instance, a PWM
backlight can be enabled and set to a specific intensity using two
operations. The order of these operations should not matter.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add driver for AST2700 to initialize DRAM in SPL.
This patch also refactors the Kconfig dependency of
Aspeed DRAM drivers as some of them are shared among
the file structures of RV and ARM ISAs.
Signed-off-by: Chia-Wei Wang <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Add the driver for the AST2700 Ibex timer, which uses CPU
cycles as the timer count running at 200MHz.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The AST2700 is the 7th generation SoC from Aspeed.
And use the driver to support clause 22 access.
Signed-off-by: Jacky Chou <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add support of Aspeed AST2700 SoC. AST2700 is based on ARM64 so modify
the DMA address related code to fit both ARM and ARM64. Besides, the
RMII/RGMII mode control register is moved from SCU500 to MAC50 so
initialize the register in ftgmac100_start correspondingly.
Signed-off-by: Jacky Chou <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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The TX/RX descriptor size is 16 byte.
When the cache line size is larger than 16 bytes, descriptors
flushed to RAM will flush more than one descriptor.
It is possible that it may mistakenly flush to other descriptor
that has been updated by MAC in RAM.
To avoid this issue, align the descriptors to cache line size.
Only one desc will be flushed or invalidated at a time.
Signed-off-by: Jacky Chou <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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The NC-SI interface does not need the MDIO bus and the
NC-SI PHY device cannot get from dm_eth_phy_connect.
Therefore, use phy_connect directly here.
Signed-off-by: Jacky Chou <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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When executing TFTP, the ARP will be replied to after receiving
the ARP. U-boot's ARP routine modifies the data in the receive
packet in response to the ARP packet and then copies it
into the transmit packet.
At this point, the received packet cache is inconsistent.
It is possible that the cache will perform a writeback action to
affect the MAC receiving packets.
Avoid the same problem that occurs in other networking protocols.
In the free_pkt function, ensure cache and memory consistency.
Signed-off-by: Jacky Chou <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Add clock controller driver for sophgo cv1800b SoC
Signed-off-by: Kongyang Liu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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As per the maintainers at egnite GmbH, they are no longer interested in
supporting this board. Go and remove the platform here. Furthermore,
this is the only AT91SAM9XE platform in-tree so remove supporting code
for that as well.
Acked-by: Nicolas Ferre <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The existing code is unnecessarily convoluted:
Arrays __prci_init_clocks_fu[5|7]40 are initialized with data.
In separate includes fu[5|7]40-prci.h the size of the arrays is provided as
constants.
By moving the structures prci_clk_fu[5|7]40 to the respective code modules
we can directly use ARRAY_SIZE() to access the size of the data used for
initialization.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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If multiple messages are written, line-feeds improve the readability.
Fixes: c40b6df87fc0 ("clk: Add SiFive FU540 PRCI clock driver")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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into next
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https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next
Various improvements to Snapdragon support:
* Bumped up the pagetable size to handle newer SoCs with much more RAM
* Made memory map parsing more robust, fixing chainloading on
SM8550/SM8650
* Populate fdt_addr_r with U-Boot's FDT by default, and set $loadaddr to
prevent
crashes with some commands which expect it
* Added initial support for SC7280/QCM6490 and the new RB3 Gen 2 board
* Add debug config fragments to enable debug UART on some SoCs.
* Enable RPMh regulators on SM8550/SM8650
* Map the cmd-db memory explicitly since it may not be in the memory map
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/22255
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Implement trivial extension to the sandbox PHY, which makes it pretend
to support selecting USB Host mode and nothing else. Any other mode is
rejected with -EINVAL. Any submode except for default submode 0 is
rejected with -EOPNOTSUPP . The implementation behaves in this trivial
way to permit easy unit testing using test which is also added in this
commit.
To run the test, use e.g. sandbox64_defconfig and run U-Boot as follows:
$ ./u-boot -Tc 'ut dm phy_setup'
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The current init operation also sets the PHY into USB host mode.
Split the mode configuration into set_mode callback instead and
implement support for device and OTG modes as well.
The OTG mode performs auto-detection and selects either host or
device mode. In case the OTG mode is configured, submode field
can be used to select full PHY (re)initialization or only mode
auto-detection. The full (re)initialization is only necessary
once, on start up.
Since the OTG mode may enable IRQ generation in the PHY, disable
that IRQ generation in the exit callback again.
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Extend generic_setup_phy() parameter list with PHY mode and submode and
call generic_phy_set_mode() in generic_setup_phy(), so the generic PHY
setup function can configure the PHY into correct mode before powering
the PHY up.
Update all call sites of generic_setup_phy() as well, all of which are
USB host related, except for DM test which now behaves as a USB host
test.
Note that if the PHY driver does not implement the .set_mode callback,
generic_phy_set_mode() call returns 0 and does not error out, so this
should not break any existing systems.
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Add device tree compatible string "renesas,rcar-gen4-rpc-if" to
the driver to match on upstream RPC DT node in R-Car Gen4 DTs.
Signed-off-by: Marek Vasut <[email protected]>
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Make sure RPC PHY timing registers are configured before performing
bus access. These registers might have been left unconfigured or may
have been configured by a prior stage bootloader and leaving them
unconfigured or misconfigured would interfere with U-Boot operation.
Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment
when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which
makes the interface operate in Serial flash or HyperFlash mode.
Signed-off-by: Marek Vasut <[email protected]>
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Make sure DRDRENR register is configured before performing external
address space read. This register might have been configured by a
prior stage bootloader and leaving it unconfigured would interfere
with U-Boot operation. Since U-Boot RPC SPI driver does not support
DDR data transfer mode yet, set this register unconditionally to 0.
Signed-off-by: Marek Vasut <[email protected]>
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Instead of writing DRDMCR with 0 first and then overwriting DRDMCR again
in case any dummy bytes have to be sent out, write DRDMCR in every case
with the amount of dummy bytes that have to be sent out. In case no dummy
bytes have to be sent out, the value written into DRDMCR is zero, so no
dummy bytes are sent out. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Instead of writing DREAR with 0 first and then overwriting DREAR again
in case of 4 byte addressing mode, write DREAR in every case once with
the correct content right away. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Add device tree compatible string "renesas,rcar-gen4-rpc-if" to
the driver to match on upstream RPC DT node in R-Car Gen4 DTs.
Signed-off-by: Marek Vasut <[email protected]>
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This soc doesn't have the generic compatible.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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We don't actually need any clocks to get UFS up and running, resets are
useful though.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Add the PM8550 & related regulators found on the SM8550 and SM8650 platforms.
The tables are imported from the Linux driver.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
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The TCS writes has no effect after the removal of the __tcs_set_trigger()
call, obviously it seems the RSC version 3 requires it to complete the transactions.
Fixes: 80c5be164ad ("soc: qcom: rpmh-rsc: drop unused multi-threading and non-active TCS support")
Signed-off-by: Neil Armstrong <[email protected]>
Tested-by: Caleb Connolly <[email protected]> # sm8250 rb5
Reviewed-by: Caleb Connolly <[email protected]>
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On at least SM8650 this region might not be included in the memory map.
Use the new mmu_map_region() helper to map it during bind().
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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memcmp() can cause aborts on some platforms and generally seems to be
the wrong approach here. Use strncmp() instead which is more correct.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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For regulator-fixed-clock, the device's private data is never set so in
fixed_clock_regulator_set_enable() is null and the function cannot
complete successfully.
Rename the _plat structure to _priv to better represent its role and set
this as the private data. As shown by the set_enable() function and by
using the same .of_to_plat hook as regulator-fixed, the platform data is
regulator_common_plat so also set .plat_auto correctly.
Finally, set up the private data by adding a .probe function to look up
the clock and set the member variable.
Fixes: f3b5100aff3 ("regulator: fixed: add possibility to enable by clock")
Signed-off-by: John Keeping <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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