| Age | Commit message (Collapse) | Author |
|---|
|
Move this group of address-related functions into a new file. These use
the flat device tree. Future work will provide new versions of these which
can support the live tree.
Signed-off-by: Simon Glass <[email protected]>
|
|
This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present
Signed-off-by: Simon Glass <[email protected]>
|
|
Please pull another update for Broadcom MIPS.
This contains new SoC's, new boards and new drivers and some bugfixes.
|
|
It's currently bugged and doesn't work for even cases.
Right shift bits instead of dividing and fix even cases.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
|
|
I missed this when I added support for BMIPS UART driver and it's needed to
achieve a real 115200 8N1 setup.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
|
|
BCM6338 has a fixed CPU frequency of 240 MHz.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
As far as I know BCM3380 has a fixed CPU frequency since I couldn't find its
PLL registers in any documentation.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
This is done in order to reuse ram size calculation for BCM6338/BCM6348
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Use a generic name for cpu_desc functions instead of using a specific SoC one.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Add a new sysreset driver that uses the recently added watchdog support.
It performs a full SoC reset by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
This driver is a simplified version of linux/drivers/watchdog/bcm63xx_wdt.c
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
To enable support for the Armada 37xx pinctrl driver, we need to
change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its
dependencies to distinguish between both platforms and drivers.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
|
|
GPIO management is pretty simple and is part of the same IP than the pin
controller for the Armada 37xx SoCs. This patch adds the GPIO support to
the pinctrl-armada-37xx.c file, it also allows sharing common functions
between the gpio and the pinctrl drivers.
Ported to U-Boot based on the Linux version by Stefan Roese.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
|
|
The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).
At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.
Ported to U-Boot based on the Linux version by Stefan Roese.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
|
|
Currently while setting the vsel value for dcdc1 and dcdc2
the driver is wrongly masking the entire 8 bits in the process
clearing PFM (bit7) field as well. Hence describe an appropriate
mask for vsel field and modify only those bits in the vsel
mask.
Source: http://www.ti.com/lit/ds/symlink/tps65218.pdf
Signed-off-by: Keerthy <[email protected]>
Fixes: 86db550b38 ("power: Add support for the TPS65218 PMIC")
Reviewed-by: Jaehoon Chung <[email protected]>
|
|
Number of blocks is a 9 bit field where 0 stands for a unlimited
number of blocks. Therefore the max number of blocks which can
be set is 511.
Signed-off-by: Heiner Kallweit <[email protected]>
|
|
Inside of
max77686_buck_volt2hex/max77686_buck_hex2volt/max77686_ldo_volt2hex we
check that the value we calculate is >= 0 however we declare 'hex' as
unsigned int making these always true. Mark these as 'int' instead. We
also move hex_max to int as they are constants that are 0x3f/0xff.
Given that the above functions are marked as returning an int, make the
variables we assign their return value to also be int to be able to
catch the error condition now. Reported by clang-3.8.
Cc: Jaehoon Chung <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
|
|
Move FTMAC100 to where it should be, alphabetically in
drivers/net/Kconfig
Signed-off-by: Tom Rini <[email protected]>
Conflicts:
drivers/net/Kconfig
|
|
|
|
LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Santan Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Santan Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Earlier when MC is loaded but DPL is not deployed results in FDT
fix-up code execution hangs. For this case now print message on
console and return success instead of return -ENODEV. This update
allows fdt fixup to continue execution.
Signed-off-by: Yogesh Gaur <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Support Andestech eth ftmac100 device tree flow on AG101P/AE3XX platform.
Verification:
Boot linux kernel via dhcp and bootm ok.
NDS32 # setenv bootm_size 0x2000000;setenv fdt_high 0x1f00000;
NDS32 # dhcp 0x600000 10.0.4.97:boomimage-310y-ae300-spi.bin
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
DHCP client bound to address 10.0.4.178 (4899 ms)
Using mac@e0100000 device
TFTP from server 10.0.4.97; our IP address is 10.0.4.178
Filename 'boomimage-310y-ae300-spi.bin'.
Load address: 0x600000
Loading: #################################################################
#################################################################
#################################################################
...
...
###################################
233.4 KiB/s
done
Bytes transferred = 13872076 (d3abcc hex)
NDS32 # dhcp 0x2000000 10.0.4.97:ae300.dtb
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
DHCP client bound to address 10.0.4.178 (4592 ms)
Using mac@e0100000 device
TFTP from server 10.0.4.97; our IP address is 10.0.4.178
Filename 'ae300.dtb'.
Load address: 0x2000000
Loading: #
82 KiB/s
done
Bytes transferred = 2378 (94a hex)
NDS32 # bootm 0x600000 - 0x2000000
Image Name:
Created: 2017-03-22 6:52:03 UTC
Image Type: NDS32 Linux Kernel Image (uncompressed)
Data Size: 13872012 Bytes = 13.2 MiB
Load Address: 0000c000
Entry Point: 0000c000
Verifying Checksum ... OK
Booting using the fdt blob at 0x2000000
Loading Kernel Image ... OK
Loading Device Tree to 01efc000, end 01eff949 ... OK
Linux version 3.10.102-20375-gb0034c1-dirty (rick@app09)
(gcc version 4.9.3 (2016-07-06_nds32le-linux-glibc-v3_experimental) )
#293 PREEMPT Wed Mar 22 14:49:28 CST 2017
CPU: NDS32 N13, AndesCore ID(wb), CPU_VER 0x0d11103f(id 13, rev 17, cfg 4159)
...
...
Signed-off-by: rick <[email protected]>
|
|
|
|
|
|
At present IDE support is controlled by CONFIG_CMD_IDE. Add a separate
CONFIG_IDE option so that IDE support can be enabled without requiring
the 'ide' command.
Update existing users and move the ide driver into drivers/block since
it should not be in common/.
Signed-off-by: Simon Glass <[email protected]>
|
|
This converts the following to Kconfig:
CONFIG_CMD_HASH
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
[trini: Rework slightly, enable on some boards again]
Signed-off-by: Tom Rini <[email protected]>
|
|
This is only used by one board and always set to 0x51. Drop this option.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This subsystem is quite old. It has been replaced with a driver-model
version (UCLASS_THERMAL). Boards are free to convert to that if required,
but here is a removal patch that could be applied in the meantime.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
This subsystem has not been converted to driver model, there is only one
driver and only one board that uses it. Drop it and its CONFIG option.
Also drop the rtc4543 RTC driver since it uses TWS.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
This option is only defined to a non-default value by canyonlands, which
needs conversion to driver model (where the I2C address would be defined
by the device tree).
Drop this option.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This converts the following to Kconfig:
CONFIG_DS4510
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This option enables a command in the driver. But the functions defined by
the driver are not called anywhere else in U-Boot. So it does not seem
useful to have this driver without its commands.
Drop this option, move the header file out of the common include/
directory and make all the function static.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This option is only used in one driver and is not enabled by any board. It
does not seem worth having the ability to remove this part of the support.
Drop the option.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This option is only used in one driver and is not enabled by any board. It
does not seem worth having the ability to remove this part of the support.
Drop the option.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This option is only used in one driver and two boards. It does not seem
worth having the ability to remove this part of the support.
Drop the option.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support
using hardware acceleration.") created entries for CONFIG_SHA1,
CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
However, no defconfig has migrated to it. Complete the move by first
adding additional logic to various Kconfig files to select this when
required and then use the moveconfig tool. In many cases we can select
these because they are required to implement other drivers. We also
correct how we include the various hashing algorithms in SPL.
This commit was generated as follows (after Kconfig additions):
[1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL
[2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL
Note:
We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously
because there is dependency between them.
Cc: Poonam Aggrwal <[email protected]>
Cc: Naveen Burmi <[email protected]>
Cc: Po Liu <[email protected]>
Cc: Shengzhou Liu <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Shaohui Xie <[email protected]>
Cc: Chunhe Lan <[email protected]>
Cc: Chander Kashyap <[email protected]>
Cc: Steve Rae <[email protected]>
Cc: Dirk Eibach <[email protected]>
Cc: Feng Li <[email protected]>
Cc: Alison Wang <[email protected]>
Cc: Sumit Garg <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: York Sun <[email protected]>
Cc: Prabhakar Kushwaha <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Akshay Saraswat <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Jagan Teki <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
Add a USB controller driver for the EHCI block in R8A7795/R8A7796 SoC.
This is a stopgap measure until we have proper DT support, clock and
reset framework in place, at which point we can switch to ehci-generic.
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Reviewed-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Support Andestech AE3xx platform: serial, timer device tree flow.
Signed-off-by: rick <[email protected]>
|
|
Support AG101P timer device tree flow.
Signed-off-by: rick <[email protected]>
|
|
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
|
|
Add driver for the Renesas Ethernet AVB block found in RCar H3/M3.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Joe Hershberger <[email protected]>
Based on work of:
Hiroyuki Yokoyama <[email protected]>
Takeshi Kihara <[email protected]>
Kazuya Mizuguchi <[email protected]>
|
|
This patch fixes to read the GPIO status after confirming the
INOUT setting.
Signed-off-by: Kouei Abe <[email protected]>
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Cc: Hiroyuki Yokoyama <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Tom Rini <[email protected]>
|
|
The mcs7830_recv() (non-DM) function discards good packets and tries to
process "bad" packets due to incorrect test condition.
Fix the condition and return the proper value as described in function
doc.
Signed-off-by: Uri Mashiach <[email protected]>
Acked-by: Igor Grinberg <[email protected]>
|
|
|
|
Add DM support for i2c functions.
Signed-off-by: Liam Beguin <[email protected]>
Signed-off-by: Sylvain Lemieux <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
|
|
Each time set_state is called, a new piece memory will
be allocated for pin_data, but not freed, this will
incur memory leak.
When error, the devm API could not free memory automatically.
So need call devm_kfree when error.
Issue reported by Coverity
Signed-off-by: Peng Fan <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Agner <[email protected]>
Cc: Stefano Babic <[email protected]>
|
