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Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards
cannot due to a hardware design decision. Select the correct driver to use
in each case.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Ajay Kumar <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Unfortunately on Pit the AP has no direct access to the tps65090 but must
talk through the EC (over SPI) to the EC's I2C bus.
When driver model supports PMICs this will be relatively easy. In the
meantime the best approach is to duplicate the driver. It will be refactored
once driver model support is expanded.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Ajay Kumar <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The driver for on-chip UART used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada <[email protected]>
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The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_SPL_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Scott Wood <[email protected]>
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Commit 3eb3e72a3f66 (nand/denali: Adding Denali NAND driver support)
introduced some new options, and some of them were documented by
commit f9860cf081ef (nand/denali: Document CONFIG symbols).
This commit allows users to enable/disable them via Kconfig
with more detailed help docs.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Scott Wood <[email protected]>
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At present sandbox has its own table of supported SPI flash chips. Now that
the SPI flash system is fully consolidated and has its own list, sandbox
should use that.
This enables us to expand the number of chips that sandbox supports.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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To add the Denali NAND driver support into U-Boot.
This driver is leveraged from Linux with commit ID
fdbad98dff8007f2b8bee6698b5d25ebba0471c9. For Denali
controller 64 variance, you need to declare macro
CONFIG_SYS_NAND_DENALI_64BIT.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Tested-by: Masahiro Yamada <[email protected]>
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The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific
and have been introduced with the Linux MTD v3.14 sync. While introducing
these functions, the length for the loop has been miscalculated. The ">> 1"
is already present in the caller. So lets remove it in the function.
Tested on omap3_ha.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Scott Wood <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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OMAP GPMC driver used with some NAND Flash devices
(e.g. Spansion S34ML08G1) causes that U-boot shows
hundreds of 'nand: bit-flip corrected' error messages.
Possible cause was discussed in the mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
The issue was partially fixed with the cc81a5291910d7a.git
however this has to be done to fix the SPL.
The original author of the code is Belisko Marek
<[email protected]>
Signed-off-by: Rostislav Lisovy <[email protected]>
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When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.
Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.
Signed-off-by: York Sun <[email protected]>
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The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.
Signed-off-by: York Sun <[email protected]>
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U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <[email protected]>
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Freescale's flash control driver is using architecture specific timer API
i.e. usec2ticks
Replace usec2ticks with get_timer() (generic timer API)
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
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[1] Move driver/core/, driver/input/ and drivers/input/ entries
from the top Makefile to drivers/Makefile
[2] Remove the conditional by CONFIG_DM in drivers/core/Makefile
because the whole drivers/core directory is already selected
by CONFIG_DM in the upper level
[3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile
[4] Simplify common/Makefile - both CONFIG_DDR_SPD and
CONFIG_SPD_EEPROM are boolean macros so they can directly
select objects
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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The macro MIN, MAX is defined as the aliase of min, max,
respectively.
Signed-off-by: Masahiro Yamada <[email protected]>
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This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Fix the following build error in case CONFIG_E1000_NO_NVM is enabled:
CC drivers/net/e1000.o
drivers/net/e1000.c: In function ‘e1000_initialize’:
drivers/net/e1000.c:5365:5: error: ‘struct e1000_hw’ has no
member named ‘eeprom_semaphore_present’
make[1]: *** [drivers/net/e1000.o] Error 1
make: *** [drivers/net] Error 2
Acked-by: Marek Vasut <[email protected]>
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- update static function
- additional debugging statements
- update "fastboot command" information
- add missing include file
- update spelling
Signed-off-by: Steve Rae <[email protected]>
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- implement 'fastboot flash' for eMMC devices
Signed-off-by: Steve Rae <[email protected]>
Acked-by: Lukasz Majewski <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5
Add support of above sgmii interfaces
Signed-off-by: Priyanka Jain <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
Cc: Jagannadha Sutradharudu Teki <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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This patch introduces the clrsetbits_le32() accessor functions in the
kirkwood SPI driver. Note that it also includes a fix:
- writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+ writel(KWSPI_SMEMRDY, &spireg->ctrl);
Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead
0xfffffffe is written into this control register. This is the main
reason to use the clrsetbits() functions now. As they make clearing
bits much less error prone.
Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and
spi_cs_deactivate() any more. Its the wrong macro but has the same
value as the correct one (KWSPI_CSN_ACT).
This is in preparation for use of this driver on the Marvell Armada XP
platform as well.
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add ID for this Numonix / STMicro chip.
Tested on Marvell DB-78460-BP board.
Signed-off-by: Stefan Roese <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
CONFIG_SF_DEFAULT_* #defines.
Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Cc: Tom Rini <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Sudhakar Rajashekhara <[email protected]>
Cc: Lokesh Vutla <[email protected]>
Cc: Vitaly Andrianov <[email protected]>
Cc: Lars Poeschel <[email protected]>
Cc: Bo Shen <[email protected]>
Cc: Hannes Petermaier <[email protected]>
Cc: Michal Simek <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <[email protected]>
Cc: Eric Benard <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Tim Harvey <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for M25PE16 and M25PX16
Cc: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Since dev->req_seq value is initialized from "reg" property of fdt node,
there is posibility, that address value contained in fdt is greater than
INT_MAX, and then value in dev->req_seq is negative which led to probe()
fail.
This patch fix this problem by ensuring that req_seq is positive, unless
it's one of errno codes.
Signed-off-by: Robert Baldyga <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Allow serial_find_console_or_panic() to work without a device tree.
Signed-off-by: Simon Glass <[email protected]>
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The sequence number support in driver model requires device tree control.
It should be skipped if CONFIG_OF_CONTROL is not defined, and should not
require functions from fdtdec.
Signed-off-by: Simon Glass <[email protected]>
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The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).
Signed-off-by: Simon Glass <[email protected]>
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Disable subpage write when using PMECC to prevent buggy partial page write.
This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)
Signed-off-by: Boris BREZILLON <[email protected]>
Acked-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.
Signed-off-by: Josh Wu <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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This driver was upstreamed without an SMSC copyright, even thought it seems
that SMSC was the original author.
See the kernel version for a code comparison:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=2f7ca802bdae2ca41022618391c70c2876d92190
It's not clear who actually moved this code, or whether the kernel was the
original source, or somewhere else, but it probably should still have the
SMSC copyright.
Signed-off-by: Simon Glass <[email protected]>
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This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD
Signed-off-by: Maxin B. John <[email protected]>
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After mtd was synced with Linux 3.14
(ff94bc40af3481d47546595ba73c136de6af6929)
the number of parameters for write_page function of nand_chip was
changed. The additional two var were needed for subpage write.
As keystone has no supbage write they are not needed. So correct
only function definition by upgrading it's parameter list.
That helps to get ritd of compilation warning.
Signed-off-by: Ivan Khoronzhuk <[email protected]>
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U-Boot has imported various source files from other projects,
mostly Linux.
Something like
#ifdef __UBOOT__
[ modification for U-Boot ]
#else
[ original code ]
#endif
is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.
Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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When network protocol errors occur (such as a file not being found on a
TFTP server), the processing done by the NetReceive() function will end
up calling the driver's .halt() implementation. However, after that the
device no longer has access to the memory buffers and will cause errors
such as this in the rtl_recv() function when trying to hand descriptors
back to the device:
pci_hose_bus_to_phys: invalid physical address
This can be fixed by deferring processing of network packets until the
descriptors have been handed back. That way rtl_halt() tearing down
network buffers is not going to prevent access to the buffers.
Reported-by: Stephen Warren <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Use size_t type for positive offsets instead of the loff_t type. The
later is defined as long long, which is larger than the pointer type
on OpenRISC architecture and therefore the following warning was
generated:
"warning: cast to pointer from integer of different size"
Signed-off-by: Vasili Galka <[email protected]>
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Use driver model for serial ports.
Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.
Signed-off-by: Simon Glass <[email protected]>
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Add driver model support so that ns16550 can support operation both with
and without driver model.
The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.
Signed-off-by: Simon Glass <[email protected]>
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The same sequence is used in several places, so move it into a function.
Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB.
Signed-off-by: Simon Glass <[email protected]>
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