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The Linux kernel v5.7-rc1 introduced the compatible "st,stm32mp15-hsotg".
See Linux kernel commit d49850110434 ("dt-bindings: usb: dwc2: add
support for STM32MP15 SoCs USB OTG HS and FS")
This patch updates the supported compatible in DWC2 driver,
removes the add-on done in U-Boot dtsi and keeps the compatible
defined in SOC dtsi arch/arm/dts/stm32mp151.dtsi:
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
...
};
Signed-off-by: Patrick Delaunay <[email protected]>
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Testing with v2021.01 on MIPS Octeon has shown, that the latest patch
for the "short packet event trb handling" did introduce a bug on
platforms with virtual address != physical address. This patch fixes
this issue by using the correct address types in the compare (both
physical in this case).
Signed-off-by: Stefan Roese <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
Cc: Ran Wang <[email protected]>
Cc: Nicolas Saenz Julienne <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Bin Meng <[email protected]>
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Function dm_pci_map_bar() may fail and returns NULL. Check this to prevent
dereferencing a NULL pointer.
In xhci-pci this may happen when board does not enable CONFIG_PCI_PNP and
PCI_BASE_ADDRESS_0 contains unconfigured zero address.
Signed-off-by: Pali Rohár <[email protected]>
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Add support to disable specific ports, it's useful for some
scenarios:
1. usb3 PHY is shared whith PCIe or SATA, the corresponding
usb3 port can be disabled;
2. some usb2 or usb3 ports are not used on special platforms,
they should be disabled to save power.
Signed-off-by: Chunfeng Yun <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- Add configuration helpers for MIPI D-PHY
- generic-phy: add configure op
- Add Amlogic AXG MIPI D-PHY driver & MIPI PCIe Analog PHY driver
- odroid: add runtime detection of the N2/N2+/C4/HC4 variants
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The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and
MIPI DSI at the same time, and provides the Analog part of MIPI DSI transmission
and Analog part of the PCIe lines.
Signed-off-by: Neil Armstrong <[email protected]>
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The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI
panels.
This D-PHY depends on a separate analog PHY.
Signed-off-by:Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
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Add the PHY configure op callback to the generic PHY uclass to permit
configuring the PHY.
It's useful for MIPI DSI PHYs to setup the link timings.
Signed-off-by:Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
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The MIPI D-PHY spec defines default values and boundaries for most of the
parameters it defines. Introduce helpers to help drivers get meaningful
values based on their current parameters, and validate the boundaries of
these parameters if needed.
These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1").
Signed-off-by: Neil Armstrong <[email protected]>
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Add support of missing I2C6_K with bit 3 of RCC_MC_APB5ENSETR =
I2C6EN: I2C6 peripheral clocks enable.
This patch allows customer to use I2C6 in SPL or in U-Boot
as other I2C instance, already support in clk driver.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Bind only the enabled GPIO subnode, to avoid to probe the node
"gpio-controller" present in SOC dtsi (disabled by default) but
not enabled in the included pincontrol dtsi file.
For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent:
gpioj: gpio@5000b000
gpiok: gpio@5000c000
Then these GPIO are absent in output of command "dm tree" and
"gpio status -a"
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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OTYPE can be used for output or for alternate function to select
PP = push-pull or OP = open-drain mode, according reference manual
(Table 81. Port bit configuration table).
This patch removes this indication for input pins and adds it
for AF and output pins for pinmux command output.
Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins")
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Instead of redefining a pin's name size, use PINNAME_SIZE defined
in include/dm/pinctrl.h
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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pin-controller pin's name must be equal to pin's name used in device
tree with "pins" DT property.
Issue detected on stm32mp157c-ev1 board with goodix touchscreen.
In DT, the goodix's pin is declared in DT with the node:
goodix_pins: goodix {
pins = "gpio14";
bias-pull-down;
};
Whereas in stmfx pin-controller driver, pin's name are equal to
"stmfx_gpioxx" where xx is the pin number.
This lead to not configure stmfx's pins at probe because pins is
identified by its name (see pinctrl_pin_name_to_selector() in
pinctrl-generic.c) and stmfx pin "gpio14" can't be found.
To fix this issue, come back to the original stmfx pin's name.
Revert "pinctrl: stmfx: update pin name"
This reverts commit 38d30cdcd65c73eeefac5efa328ad444a53b77dd.
Signed-off-by: Patrice Chotard <[email protected]>
Tested-by: Patrick DELAUNAY <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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- Espressobin: Set default env values at runtime (Pali)
- Espressobin: Set the maximum slave SPI speed to 40MHz (Pali)
- theadorable: PCIe test code enhancement and early deemphasis
enabling (Stefan)
- pci_mvebu: Disable config access to PCI host bridge ports (Stefan)
- mv_sdhci: parse device-tree entry (Baruch)
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Layerscape: Enable gpio
Bug fixes & updates related to dspi, qspi, pciep, SVR mask,
stream-id, env variables, mdio for LAyerscape Platforms
Add SATA, network variant 1, 2 support on sl28
powerpc: T1042: drop CONFIG_VIDEO, Add kmcent2 board supporrt, keymile
Bug fixes and updates for keymile, Kontron
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Update gpio driver to use same logic for big-endian and little-endian
Signed-off-by: Biwen Li <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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LX2162A is not like LX2160A which has different PCIe controller
in rev1 and rev2 silicon. It supports only one configuration of
PCIe controller, which is same as LS2088A. So update PCIe
compatible string same as LS2088A.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Wasim Khan <[email protected]>
Tested-by: Wasim Khan <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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This patch moves the SVR definitions to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Wasim Khan <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL
workaround as the LS208x and also has a 64 byte TX buffer.
With the previous settings SPI-NAND reads over AHB were
corrupted.
Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API")
Signed-off-by: Mathew McBride <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Adapted from kernel commit b0177aca7aea
From: Michael Walle <[email protected]>
Make use of a core helper to ensure the desired width is respected
when calling spi-mem operators.
Otherwise only the SPI controller will be matched with the flash chip,
which might lead to wrong widths. Also consider the width specified by
the user in the device tree.
Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller")
Signed-off-by: Michael Walle <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Signed-off-by: Mathew McBride <[email protected]> [adapt for U-Boot]
Reviewed-by: Priyanka Jain <[email protected]>
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Current MDIO wait time is too long, which introduce long delay when
PHY negotiation register checking. Reduce it to 10us
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Fugang Duan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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We have encountered circumstances when a board design does not include
pull-up resistors on the external MDIO buses which are not used. This
leads to the MDIO data line not being pulled-up, thus the MDIO controller
will always see the line as busy.
Without a timeout in the MDIO bus driver, the execution is stuck in an
infinite loop when any access is initiated on that external bus.
Add a timeout in the driver so that we are protected in this
circumstance. This is similar to what is being done in the Linux
xgmac_mdio driver.
Signed-off-by: Ioana Ciornei <[email protected]>
Reviewed-by: Madalin Bucur <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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Provide an explicit configuration option to disable default "unlock all"
of any flash chip which supports locking. It doesn't make sense to
automatically unprotect the entire flash on each u-boot startup if the
block protection bits are actually used.
Traditionally, the unlock was there to be able to write to flash devices
which powered-up with the block protection bits set. Over time this
feature creeped into all flash devices which support locking.
For a more detailed description and discussion see:
https://lore.kernel.org/linux-mtd/[email protected]/
Keep things simple in u-boot and just provide a configration option to
disable this behavior which can be set per board.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Call mmc_of_parse() so that generic DT properties like 'non-removable'
are taken into account.
This fixes boot on Clearfog with eMMC on SOM that requires the
non-removable property.
Reported-by: Thorsten Spille <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
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This patch changes the PCI config routines in the Armada XP / 38x driver
to not allow access to the PCIe root ports.
While updating the Armada XP based theadorable to the latest mainline
and testing it with the DM PCI driver I noticed, that the PCI root
bridge was being configured incorrectly. Resulting in the PCIe Intel
WiFi was not working correctly in Linux. With this patch applied, all
PCIe devices work without any issues in Linux again.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Marek Behún <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: Mario Six <[email protected]>
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In case MMC has MBR system and fastboot writes GPT,
MMC is still recognized as MBR.
Invoke part_init() to purge cached data and update
information about partition table type.
Signed-off-by: Roman Stratiienko <[email protected]>
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Add command oem bootbus which executes the command
``mmc bootbus <id> <arg>`` on the current fastboot mmc device
(<i> = CONFIG_FASTBOOT_FLASH_MMC_DEV) to set the eMMC boot
configuration on first update, with
<arg> = boot_bus_width reset_boot_bus_width boot_mode
$> fastboot oem bootbus:<boot_bus_width> <reset_boot_bus_width> <boot_mode>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add fastboot command oem partconf which executes the command
``mmc partconf <id> <arg> 0`` on the current <id> mmc device
to configure the eMMC boot partition with
<arg>: boot_ack boot_partition, so the command is:
$> fastboot oem partconf:<boot_ack> <boot_partition>
The partition_access argument is forced to 0 (userdata)
Signed-off-by: Patrick Delaunay <[email protected]>
[lukma - Kconfig adjustments after merging this patch]
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Update the code and the configs for eMMC boot and userdata
partitions acces
- FASTBOOT_MMC_BOOT_SUPPORT: boot partition 1 and 2 (erase/write)
- FASTBOOT_MMC_BOOT1_NAME: boot partition 1, default name="mmc0boot0"
- FASTBOOT_MMC_BOOT2_NAME: boot partition 2, default name="mmc0boot1"
This patch also removes the unnecessary dependency with
ARCH_MEDIATEK and EFI_PARTITION.
Signed-off-by: Patrick Delaunay <[email protected]>
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Split userdata and boot partition support for eMMC update
and correct the description (update is supported).
The new configuration CONFIG_FASTBOOT_MMC_USER_SUPPORT
allows to activate support of userdata partition update,
based on target name=CONFIG_FASTBOOT_MMC_USER_NAME
This patch also removes the unnecessary dependency with
ARCH_MEDIATEK and EFI_PARTITION.
Signed-off-by: Patrick Delaunay <[email protected]>
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It is possible to implement fastboot_set_reboot_flag in a generic way
if BCB commands are turned on for a target. Using
bcb_set_reboot_reason allows to do this by simply passing string with
correct reboot reason that should be handled during next boot process.
If BCB are turned off, then bcb_set_reboot_reason would simply return
error, so it won't introduce any new behaviour for such targets.
Signed-off-by: Roman Kovalivskyi <[email protected]>
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This reverts commit 0ebf9842e56c5b8cb7cb1f990bb452cc14af6225.
Current generic implementation of fastboot_set_reboot_flag is somewhat
messy and requires some additional configuration option to be enabled
besides CMD_BCB, so it reverts that implementtion in order to bring a
new cleaner one.
Next commit introduces new generic implementation of
fastboot_set_reboot_flag.
Signed-off-by: Roman Kovalivskyi <[email protected]>
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For printing unsigned int %u has to be used.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Sync DTS from Linux kernel for all K3 platforms
- Add MMC higher speed nodes for AM65x, J721e, J7200
- Convert Nokia RX-51 to use CONFIG_DM_MMC
- Minor fixes for LEGO MINDSTORMS
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Use the generic sdhci_set_control_reg() instead of duplicating
in platform driver.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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With the new SW tuning App note[1], a custom tuning algorithm is
required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
involves running through the 32 possible input tap delay values and
sending the appropriate tuning command (CMD19/21) for each of them
to get a fail or pass result for each of the values. Typically, the
range will have a small contiguous failing window. Considering the
tuning range as a circular buffer, the algorithm then sets a final
tuned value directly opposite to the failing window.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Add support for writing new clock buffer select property for both
the am654x and j721e 4 bit IPs
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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DLL need only be enabled for speed modes and clock frequencies at or
above 50 MHz. For speed modes that don't enable the DLL, we need to
configure a static input delay value. This involves reading an optional
itap-del-sel-* value from the device tree and configuring it for the
appropriate speed mode.
Therefore, move all dll configurations to their own functions and gate it
with 50 MHz speed and a minimum mode. If both these conditions are not
satisfied then configure delay chain modes.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Add Support for AM65x PG2.0. Use the SoC bus framework to fixup
the platform data and do DLL calibration if the revision is 1.0
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB
flag to indicate the same.
Also move the write of trm_icp and driver strength to the set_clock()
function to match the kernel configuration flow.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Convert the flags field defines to use the BIT() macro.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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There are some speed modes that work without switching the dll on.
Unconditionally switch off the DLL before setting clock frequency to
support this case. The software will automatically enable DLL for speed
modes that require it. This also means the dll_on priv data member is no
longer required.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Add a set_voltage() function which handles the switch from 3.3V to 1.8V
for SD card UHS modes.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The K3 R5F remoteproc driver in U-Boot was upstreamed prior to the
equivalent remoteproc driver in the Linux kernel. Some of the DT
properties used in U-Boot got upstreamed using different names
in Linux kernel.
The modified property names include the R5F cluster mode configuration
property "lockstep-mode"; and three different individual R5F core config
properties - "atcm-enable", "btcm-enable" and "loczrama". The property
names were updated as follows:
lockstep-mode => ti,cluster-mode
atcm-enable => ti,atcm-enable
btcm-enable => ti,btcm-enable
loczrama => ti,loczrama
Update the K3 R5F remoteproc driver, the corresponding binding, and
all the existing usage in AM65x, J721E and J7200 dts files all at
once to use the new properties and to not break any bisectability.
Signed-off-by: Suman Anna <[email protected]>
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The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It
also doesn't allow the zynqmp_gqspi driver to calculate the correct
number of dummy cycles for some NOR ops (as doing so also requires the
buswidth).
Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us
the buswidth values to correctly support all SNOR_PROTO_X_X_X commands
and to properly calculate dummy cycles.
Signed-off-by: Brandon Maier <[email protected]>
CC: [email protected]
CC: [email protected]
CC: Ashok Reddy Soma <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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sandbox_scmi_devices_ctx() may return NULL. We should not dereference this
value in sandbox_scmi_devices_remove().
The problem was indicated by 'gcc-11 -fanalyzer'.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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priv->iobase was declared as phys_addr_t which is now a 64-bit
address. In a 32-bit build, this causes the following warning
seen when building ftmac100.c:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Cast priv->iobase with uintptr_t.
Signed-off-by: Bin Meng <[email protected]>
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dev_read_addr() returns fdt_addr_t which is now a 64-bit address.
In a 32-bit build, this causes the following warning seen when
building serial_sifive.c:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Cast the return value with uintptr_t.
Signed-off-by: Bin Meng <[email protected]>
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