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The EMAC driver contains a lot of magic bits, although the manuals
and the Linux driver have all names for them.
Define those names and use them when programming the registers.
Also this replaces a lot of readl/mask/writel operations with the much
easier-to-read setbits_le32() macro.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Apparently due to copying from some older or converted driver, the
sun8i_emac driver contains pointless wrapper functions to bridge
between a legacy driver and the driver model.
Since sun8i_emac is (and always was) driver model only, there is no
reason to have those confusing wrappers. Just remove them, and use
the driver model prototypes directly.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When preparing the register value for the MDIO command register, we
start with a zeroed register, so there is no need to mask off certain
bits before setting them.
Simplify the sequence, and rename the variable to a more matching
mii_cmd on the way.
Also the open-coded time-out routine can be replaced with a much safer
and easier-to-read call to wait_for_bit_le32().
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When initialising the TX DMA descriptors, we mostly chain them up,
but of course don't know about any data or its length yet.
That means they are still invalid, and the OWN bit should NOT be set
yet.
In fact when we later tell the MAC about the beginning of the chain,
and enable TX DMA in the start() routine, the MAC will start fetching
TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA
and TX_DMA_CUR_DESC registers.
Clear the owner bit, to not give the MAC the wrong illusion that it
owns the descriptors already.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When phy_startup() returns with an error, because there is no link or
the user interrupted the process, we shall stop the _start() routine
and return with an error, instead of proceeding anyway.
This fixes pointless operations when there is no Ethernet cable
connected, for instance.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
as its value is IP dependent and not arch dependent
No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops").
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of
struct mmc_config from devicetree.
The same logic is duplicated in stm32_sdmmc2_probe(). Use
mmc_of_parse(), which is more generic.
Signed-off-by: Alexandru Gagniuc <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no
additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed"
is used for MMC HS at both 26MHz and 52MHz.
Use the same approach and enable MMC_CAP(MMC_HS_52) host capability
when "cap-mmc-highspeed" is found in the devicetree. In the event an
MMC card doesn't support 52 MHz, it will be clocked at a speed based
on its EXT CSD, even on 52 MHz host controllers
Signed-off-by: Alexandru Gagniuc <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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- Assorted R-Car Gen3 updates
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Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
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Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
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This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
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This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
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Add RPC entry into the R8A774A1 clock driver tables.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
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Add fallback compatibility string for R-Car Gen3 and RZ/G2.
Also sorted the compatible string as per SoC ID.
Signed-off-by: Biju Das <[email protected]>
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Add an entry in usb_gadget_controller_number() for the MTU3
gadget controller. It is used to bind the USB Ethernet driver.
Signed-off-by: Chunfeng Yun <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This patch adds support for the MediaTek USB3 DRD controller,
its host side is based on xHCI, this driver supports device mode
and host mode.
Signed-off-by: Chunfeng Yun <[email protected]>
Acked-by: Bin Meng <[email protected]>
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There is only declaration of usb_speed_string(), but no definition,
so add it to avoid build error when call it.
Signed-off-by: Chunfeng Yun <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add enum USB_SPEED_SUPER_PLUS for USB3.1
Signed-off-by: Chunfeng Yun <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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%s/Occured/Occurred/
Signed-off-by: Naoki Hayama <[email protected]>
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In buffer DMA mode, gadget should re-configure EP 0 to received SETUP
packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes)
and EP 0 is in WAIT_FOR_SETUP state.
Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT
received from RxFifo and wriiten to the external memory.
Signed-off-by: Chance.Yang <[email protected]>
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void * can be assigned to any pointer variable. Avoid unnecessary
conversions.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features for 2021.01 cycle:
This feature set brings the rework of the clock tree for sam9x60 SoC.
This makes the clock tree fully compatible with Common Clock Framework
and allows full clock configuration in U-Boot. This means that the
sam9x60 boards can boot now using U-Boot.
This also includes the definitions for sam9x60 SiPs and a divisor fix
for the clock on sama7g5 SoC.
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This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: Mihai Sain <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
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clk-master can have 5 divisors with a field width of 3 bits
on some products.
Change the mask and number of divisors accordingly.
Reported-by: Mihai Sain <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
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Add SAM9X60 clock support compatible with CCF.
Signed-off-by: Claudiu Beznea <[email protected]>
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Done with:
./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Done with:
./tools/moveconfig.py VIDEO_BMP_RLE8
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Done with:
./tools/moveconfig.py VIDEO_BMP_GZIP
The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN
are not activated in these defconfigs:
- trats_defconfig
- s5pc210_universal_defconfig
- trats2_defconfig
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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For levels equal to the maximum value, the duty cycle must be equal to
the period.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The description of the 'max_level' field was incorrectly assigned to the
'min_level' field.
Signed-off-by: Dario Binacchi <[email protected]>
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The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.
This is based on the Linux commit [1] and adapted to the U-Boot driver.
[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")
Signed-off-by: Neil Armstrong <[email protected]>
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The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.
To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.
This is based on the Linux commit [1] and adapted to the U-Boot driver.
[1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings")
Signed-off-by: Neil Armstrong <[email protected]>
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- Fix Octeon SPI driver for Octeon TX2
- Fix and enhance Octeon watchdog driver
- Misc minor enhancements to Octeon TX/TX2
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Necessary for dev_xxx.
Signed-off-by: Tom Rini <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Tom Rini <[email protected]>
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This driver doesn't use DM (in the correct places), so we use a device and
not a udevice. We also need to include device_compat.h
Signed-off-by: Sean Anderson <[email protected]>
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This was included, but was ifdef'd out. We also need dm.h for struct
udevice.
Signed-off-by: Sean Anderson <[email protected]>
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This header is necessary for the dev_xxx macros.
Signed-off-by: Sean Anderson <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.
Signed-off-by: Suneel Garapati <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Suneel Garapati <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
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Remove a left-over debug test message from the Octeon TX / TX2
MMC driver.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Suneel Garapati <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
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Octeon TX2 sets the TB100_EN bit in the config register. We need to use
a fixed 100MHz clock for this as well to work properly.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Suneel Garapati <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
Cc: Jagan Teki <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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This includes device_compat.h, and fixes several calls to dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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