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2020-09-24drivers: net: phy: Use Aquantia driver for AQR113CMadalin Bucur
Add support for AQR113C PHY Signed-off-by: Madalin Bucur <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2020-09-24drivers: net: ldpaa_eth: lx2160a: fix bug in checking if a DPMAC is enabledGrigore Popescu
The next DPMAC was always verified if it is enabled. In case of DPMAC@6, the DPMAC@7 is verified. As DPMAC@7 is disabled, DPMAC@6 will be considered disabled and not detected by uboot. Signed-off-by: Grigore Popescu <[email protected]> Signed-off-by: Ioana Ciornei <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2020-09-24Merge tag 'xilinx-for-v2021.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.01 arm64: - Support for bigger U-Boot images compiled with PIE microblaze: - Extend support for LE/BE systems zynqmp: - Refactor silicon ID detection code with using firmware interface - Add support for saving variables based on bootmode zynqmp-r5: - Fix MPU mapping and defconfig setting. xilinx: - Minor driver changes: names alignment - Enable UBIFS - Minor DT and macros fixes - Fix boot with appended DT - Fix distro boot cmd: - pxe: Add fixing for platforms with manual relocation support clk: - fixed_rate: Add DM flag to support early boot on r5 fpga: - zynqmppl: Use only firmware interface and enable SPL build serial: - uartlite: Enable for ARM systems and support endians mmc: - zynq: Fix indentation net: - gem: Support for multiple phys - emac: Fix 64bit support and enable it for arm64 kconfig: - Setup default values for Xilinx platforms - Fix dependecies for Xilinx drivers - Source board Kconfig only when platform is enabled - Fix FPGA Kconfig entry with SPL - Change some defconfig values bindings: - Add binding doc for vsc8531
2020-09-24net: tsec: Add the compatible string "gianfar" supportHou Zhiqiang
Add compatible string "gianfar" support and update the device-tree-bindings doc. Signed-off-by: Hou Zhiqiang <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2020-09-24net: tsec: Add fixed-link PHY supportHou Zhiqiang
The info of fixed-link PHY is described in DT node instead of getting from MII, so detect the fixed-link PHY DT node first, if it doesn't exist then probe the MII. Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> [Rebased] Signed-off-by: Priyanka Jain <[email protected]>
2020-09-24net: tsec: convert to use DM_MDIO when DM_ETH enabledHou Zhiqiang
For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO. Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing otherwise. Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> [Reworked to fix gazerbeam config] Signed-off-by: Priyanka Jain <[email protected]>
2020-09-24net: fsl_mdio: Correct the MII management register block addressHou Zhiqiang
The MII management register block offset is different between gianfar and etsec2 compatible devices, this patch is to fix this issue by adding driver data for different compatible string. Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support") Signed-off-by: Hou Zhiqiang <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2020-09-24net: fsl_mdio: Change to use virtual addressHou Zhiqiang
Use virtual address to access the MII block registers instead of physical address. Signed-off-by: Hou Zhiqiang <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2020-09-24phy: make phy_connect_fixed work with a null mdio busVladimir Oltean
It is utterly pointless to require an MDIO bus pointer for a fixed PHY device. The fixed.c implementation does not require it, only phy_device_create. Fix that. Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2020-09-24arm64: a37xx: pci: Disable link training when unloading driverPali Rohár
As required by PCI Express spec a delay for at least 100ms after de-asserting PERST# signal is needed before link training is enabled. Linux kernels prior to 5.8 version do not automatically disable link training before de-asserting PERST# signal, therefore this requirement is not fulfilled. Above requirement is needed for proper detection of some Compex PCIe WiFi cards. Otherwise Linux kernel cannot detect it. To allow using those PCIe cards with older Linux kernel versions booted by U-Boot compiled with U-Boot a37xx pci driver, disable link training in U-Boot when unloading this pci driver. Thanks to DM_FLAG_OS_PREPARE flag, U-Boot automatically unload this driver when booting Linux kernel. Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2020-09-24mtd: spi-nor-ids: add support for Macronix mx25u12835f flashVladimir Vid
Some of Marvell A3700 boards use mx25u12835f, specifically uDPU and ESPRESSObin v7. Signed-off-by: Vladimir Vid <[email protected]> [a.heider: adapt commit message to mainline] Signed-off-by: Andre Heider <[email protected]>
2020-09-23pci: layerscape: Fix spurious writes and panicMichael Walle
The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI root devices are layerscape PCIe controllers. Unfortunately, this is not true for the LS1028A. There is one additional static PCI root complex (this contains the networking devices) which has nothing to do with the layerscape PCIe controllers. On recent U-Boot versions this results in the following panic: "Synchronous Abort" handler, esr 0x96000044 elr: 000000009602fa04 lr : 000000009602f9f4 (reloc) elr: 00000000fbd73a04 lr : 00000000fbd739f4 x0 : 0080000002000101 x1 : 0000000000000000 x2 : 00000000fbde9000 x3 : 0000000000000001 x4 : 0000000000000000 x5 : 0000000000000030 x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0 x8 : 0000000000000002 x9 : 000000000000000c x10: 00000000ffffffe8 x11: 0000000000000006 x12: 000000000001869f x13: 0000000000000a2c x14: 00000000fbb3d2cc x15: 00000000ffffffff x16: 0000000000010000 x17: 0000000000000000 x18: 00000000fbb3fda0 x19: 0000000000000800 x20: 0000000000000000 x21: 00000001f0000000 x22: 0000000000000800 x23: 0000000000000009 x24: 00000000fbdc3c1b x25: 00000000fbdc28e5 x26: 00000000fbdcc008 x27: 00000000fbdc16e2 x28: 000000000f000000 x29: 00000000fbb3d3a0 Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814) Resetting CPU ... This bug already existed in former versions, but the spurious write was never trapped, because the destination address was a valid address (by pure luck). Make sure the PCI root is actually one of the expected PCIe layerscape controllers by matching its compatible string. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Tested-by: Heiko Thiery <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2020-09-23clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flagMichal Simek
fixed-rate driver is not different from clk_fixed_factor and it is required very early in boot that's why setup flag for it. Signed-off-by: Michal Simek <[email protected]>
2020-09-23mmc: zynq: Fix incorrect indentationMichal Simek
Trivial fix. Fixes: d1f4e39d58db ("mmc: zynq_sdhci: Add support for SD3.0" Signed-off-by: Michal Simek <[email protected]>
2020-09-23fpga: zynqmp: Protect zynqmp_loads() for SPLMichal Simek
if conditions should match. Fixes: a18d09ea384f ("fpga: zynqmp: Add secure bitstream loading for ZynqMP") Signed-off-by: Michal Simek <[email protected]>
2020-09-23fpga: kconfig: Rename SPL_FPGA_SUPPORT to SPL_FPGAMichal Simek
The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile and zynqmp.c to simplify if/endif logic in zynqmp.c. This change is mostly done to be able to use CONFIG_IS_ENABLED macro and obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync. And removing one line from Topic Miami boards which is not needed because symbol is not enabled via Kconfig. Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-23fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macrosMichal Simek
There is no need to use these macros because enum pm_api_id can be used instead. Signed-off-by: Michal Simek <[email protected]>
2020-09-23net: xilinx: axi_emac: Typecast flush_cache argumentsAshok Reddy Soma
flush_cache() arguments are not type casted to take care of 64 bit systems. Use phys_addr_t to type cast for it to work properly for 32 bit and 64 bit systems. Signed-off-by: Ashok Reddy Soma <[email protected]> Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Ramon Fried <[email protected]>
2020-09-23net: xilinx: axi_emac: Fix dma descriptors for 64bit and compilation warningsAshok Reddy Soma
There are compilation warnings showing up when we compile AXI ethernet driver for 64bit architectures. Fix them, so that it works on both 32 and 64 bit architectures. DMA descriptors are not taking care of 64bit addresses. To fix it, change axidma_bd members as below: next ==> next_desc reserverd1 ==> next_desc_msb phys ==> buf_addr reserverd2 ==> buf_addr_msb and update next_desc and buf_addr with lower 32 bits of the addresses, update next_desc_msb and buf_addr_msb with upper 32 bits of the 64bit addresses. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Ramon Fried <[email protected]>
2020-09-23nand: Kconfig: Change dependency for NAND_ARASANMichal Simek
NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with !DM that's why Kconfig it showing it as error: WARNING: unmet direct dependencies detected for DM_MTD Depends on [n]: DM [=n] Selected by [y]: - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2020-09-23serial: uartlite: Add support to work with any endiannessT Karthik Reddy
This endinness changes are taken from linux uartlite driver. Reset TX fifo in control register and check TX fifo empty flag in lower byte of the status register to detect if it is a little endian system. Based on this check, program the registers with le32 or be32 through out the driver. Signed-off-by: T Karthik Reddy <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2020-09-23xilinx: kconfig: Change Kconfig dependencies for Xilinx driversMichal Simek
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in PL and vice versa. That's why change dependencies and do not limit enabling just for some platforms. This is follow up patch based on commit 664e16ce99a0 ("xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers"). Signed-off-by: Michal Simek <[email protected]>
2020-09-23net: gem: Add support for more PHYs on MDIO busMichal Simek
Find out MDIO bus and enable MDIO access to it if this is done via different GEM controller. Only works across GEM instances. Signed-off-by: Michal Simek <[email protected]>
2020-09-23xilinx: drivers: Use '_' instead of '-' in driver nameMichal Simek
The most of drivers are using '_' instead of '-' in driver name. That's why sync up these names to be aligned. It looks quite bad to see both in use. It is visible via dm tree command. Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-23pinmux: pic32: add SDHCI pin configJohn Robertson
The GPIO pins used by the SDHCI controller need to be configured to allow the interface to work. Signed-off-by: John Robertson <[email protected]>
2020-09-23mmc: pic32: Refresh PIC32 MMC driverJohn Robertson
The existing driver is not compatible with the Driver Model. This patch makes the necessary changes while also removing obsolescent calls/properties as follows: - fdtdec_* calls replaced with dev_read_* equivalents; - 'clock-freq-min-max' property replaced by querying the frequency of the source clock 'base_clk'; - The card detect erratum workaround is applied during probe rather than overriding get_cd. The card detect workaround (Microchip ref. DS80000736E, erratum #15) is not always needed and can be disabled using a vendor specific DT property. Signed-off-by: John Robertson <[email protected]>
2020-09-22dm: add cells_count parameter in live DT APIs of_parse_phandle_with_argsPatrick Delaunay
In the live tree API ofnode_parse_phandle_with_args, the cell_count argument must be used when cells_name is NULL. But this argument is not provided to the live DT function of_parse_phandle_with_args even it is provided to fdtdec_parse_phandle_with_args. This patch adds support of the cells_count parameter in dev_ and of_node API to allow migration and support of live DT: - of_parse_phandle_with_args Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-22dm: syscon: typo aleradyHeinrich Schuchardt
* Fix typo: %s/alerady/already/. * Add missing 'the'. * Reformat a comment. Signed-off-by: Heinrich Schuchardt <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-22gpio/mpc83xx_spisel_boot.c: include log.hRasmus Villemoes
Fix build failure, it used to get this implicitly through common.h until f7ae49fc4f (common: Drop log.h from common header). Signed-off-by: Rasmus Villemoes <[email protected]> Reviewed-by: Heiko Schocher <[email protected]>
2020-09-22spi: mpc8xxx_spi.c: fix cs activate/deactivateRasmus Villemoes
Somewhere between v2020.04 and v2020.07 the mpc8xxx_spi driver broke, I'm guessing due to this hunk @@ -559,6 +560,8 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags) if (ret) return ret; + /* combine the requested flags (for IN/OUT) and the descriptor flags */ + flags |= desc->flags; ret = _dm_gpio_set_dir_flags(desc, flags); from commit 695e5fd5469a ("gpio: update dir_flags management"). But the blame is mostly on the driver itself which seems rather confused: The chip select gpios are requested with GPIOD_ACTIVE_LOW, but then in each activate/deactivate, dm_gpio_set_dir_flags() is called with merely GPIOD_IS_OUT, and then the driver call set_value(0) for activate. That used to work, but with the above hunk, the ACTIVE_LOW setting from the request becomes persistent, so the gpio driver ends up being asked to set the value to 1 in mpc8xxx_spi_cs_activate(). So drop the dm_gpio_set_dir_flags() calls in the activate/deactivate functions, and use a value of 1 to mean "logically enabled". Ideally, I think we should also drop the GPIOD_ACTIVE_LOW from the request and make it up to the list of gpio cs in DT to indicate whether that CS is enabled when driven low (as is of course usually the case), but that requires changing arch/powerpc/dts/gdsys/gazerbeam-base.dtsi among others, and I don't have that hardware to test on. I have, however, tested our own (mpc8309-based) hardware with this change, and I have also tested that removing the GPIOD_ACTIVE_LOW from the request and updating our DT as - gpios = <&spisel 0 0>; + gpios = <&spisel 0 GPIO_ACTIVE_LOW>; still works. Signed-off-by: Rasmus Villemoes <[email protected]>
2020-09-22clk: at91: sama7g5: add clock supportClaudiu Beznea
Add clock support for SAMA7G5. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: pmc: add generic clock opsClaudiu Beznea
Add generic clock ops to be used by every AT91 PMC driver built on top of CCF. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-generic: add driver compatible with ccfClaudiu Beznea
Add clk-generic driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-peripheral: add driver compatible with ccfClaudiu Beznea
Add clk-peripheral compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-system: add driver compatible with ccfClaudiu Beznea
Add clk-system driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-programmable: add driver compatible with ccfClaudiu Beznea
Add clk-programmable driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-utmi: add support for sama7g5Claudiu Beznea
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via XTALF register. Values written at bits 2..0 in this register correspond to the on board crystal oscillator frequency. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-utmi: add driver compatible with ccfClaudiu Beznea
Add clk-utmi driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-master: add support for sama7g5Claudiu Beznea
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has multiple master clocks feeding different subsystems. One of them feeds image subsystem and is changeable based on image subsystem needs. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-master: add driver compatible with ccfClaudiu Beznea
Add clk-master driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: sam9x60-pll: add driver compatible with ccfClaudiu Beznea
Add sam9x60-pll driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: clk-main: add driver compatible with ccfClaudiu Beznea
Add clk-main driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: sckc: add driver compatible with ccfClaudiu Beznea
Add sckc driver compatible with common clock framework. Driver implements slow clock support for SAM9X60 compatible IPs (in this list it is also present SAMA7G5's slow clock IP). Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: move clock code to compat.cClaudiu Beznea
Move clock code to compat.c to allow switching to CCF without mixing CCF code with non CCF code. This prepares the field for next commits. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: at91: pmc: add helpers for clock driversClaudiu Beznea
Add helper for clock drivers. These will be used by following commits in the process of switching AT91 clock drivers to CCF. Signed-off-by: Claudiu Beznea <[email protected]>
2020-09-22clk: get clock pointer before proceedingClaudiu Beznea
clk_get_by_indexed_prop() retrieves a clock with dev member being set with the pointer to the udevice for the clock controller driver. But in case of CCF each clock driver has set in dev member the reference to its parent (the root of the clock tree is a fixed clock, every node in clock tree is a clock registered with clk_register()). In this case the subsequent operations like dev_get_clk_ptr() on clocks retrieved by clk_get_by_indexed_prop() will fail. For this, get the pointer to the proper clock registered (with clk_register()) using clk_get_by_id() before proceeding. Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-22clk: do not disable clock if it is criticalClaudiu Beznea
Do not disable clock if it is a critical one. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-22clk: bind clk to new parent deviceClaudiu Beznea
Clock re-parenting is not binding the clock's device to its new parent device, it only calls the clock's ops->set_parent() API. The changes in this commit re-parent the clock device to its new parent so that subsequent operations like clk_get_parent() to point to the proper parent. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-22dm: core: add support for device re-parentingClaudiu Beznea
In common clock framework the relation b/w parent and child clocks is determined based on the udevice parent/child information. A clock parent could be changed based on devices needs. In case this is happen the functionalities for clock who's parent is changed are broken. Add a function that reparent a device. This will be used in clk-uclass.c to reparent a clock device. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2020-09-22clk: check hw and hw->dev before dereference itClaudiu Beznea
Check hw and hw->dev before dereference it. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Simon Glass <[email protected]>
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