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Define default values for input and output clock phase delays for
Versal. Also define functions for setting tapdelays based on these
clock phase delays.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Define and use functions for setting input and output tapdelays
based on clk phase delays.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Define input and output clock phase delays with pre-defined values.
Define arasan_sdhci_clk_data type structure and add it to priv
structure and store these clock phase delays in it.
Read input and output clock phase delays from dt. If these values are
not passed through dt, use pre-defined values.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Just group macros below headers. Other patches will be using this location
too.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace speed macro's used with these new timing
macro's wherever applicable.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830.
This is partial revert of the above commit.
mmc_of_parse() is reading no-1-8-v from device tree and if set,
it is clearing the UHS speed capabilities of cfg->host_caps.
cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 |
MMC_MODE_HS400 | MMC_MODE_HS400_ES);
This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104,
SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50.
Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(),
these speed flags are getting set again in cfg->host_caps in
sdhci_setup_cfg().
The reason for this is, SDHCI_SUPPORT_XXX flags are cleared
only if controller is not capable of supporting MMC_VDD_165_195 volts.
if (caps & SDHCI_CAN_VDD_180)
cfg->voltages |= MMC_VDD_165_195;
if (!(cfg->voltages & MMC_VDD_165_195))
caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
It means "no-1-8-v", which is read from DT is not coming in to effect.
So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to
clear UHS speeds based on no-1-8-v from device tree.
Hence revert the functionality related to no-1-8-v only, rest is fine
in the patch.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect.
Fix zqspi to priv in function descriptions.
Change the description of priv as pointer to zynq_qspi_priv structure.
Fix other function descriptions to kernel-doc style.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Use tabs to be aligned with the rest of the code.
Fixes: 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support")
Signed-off-by: Michal Simek <[email protected]>
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There is no reason to have ZYNQ specific Kconfig macro in generic location
to be visible for all other SoCs. That's why move it to Xilinx common
location to be visible only for us.
Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to
disable it or enable. This has connection to code which is reading the
whole content of i2c and also work with the rest of date not just with MAC
address.
Signed-off-by: Michal Simek <[email protected]>
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Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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There also a need to check return values to make sure that clocks were
enabled and setup properly.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for getting a node/property from aliases.
The similar functionality is provided for chosen node and this
implemenatation is copy of it.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Remove unused variable 'count' which is causing warning while
compilation.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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In case of fpga loading (which can be huge) 100ms is not enough. That's why
extend timeout 10 times to wait maximum 1s to get ACK back.
Signed-off-by: Michal Simek <[email protected]>
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Don't know reason but in regular flow addr_hi/low are swapped in ATF. It
means when fpga load is done from EL3 there is a need to swap it for PMUFW
to load bitstream.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Remove unused variable:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:254:18: warning: unused variable 'timeout' [-Wunused-variable]
254 | u32 reg, count, timeout;
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Fixes: 0c0de58f7b30 ("spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function")
Signed-off-by: Michal Simek <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-video
- disable CONFIG_VIDEO to remove DM conversion warnings
for boards: at91sam9, eb_cpu5282, ls1021aqds, ls1021atwr,
mx23evk, mx6sxsabresd, mx7dsabresd, nokia_rx51, picosam9g45,
sansa_fuze_plus, xfi3
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Disable VIDEO config to fix DM_VIDEO conversion
deadline warning.
Signed-off-by: Anatolij Gustschin <[email protected]>
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Remove CONFIG_VIDEO dependency to fix board removal warnings.
Signed-off-by: Anatolij Gustschin <[email protected]>
Cc: Jens Scharsig <[email protected]>
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Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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This matches the naming scheme of other timer drivers.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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This is a regular timer driver, and should live with the other timer
drivers.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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free() checks if its argument is NULL. No need to check it twice.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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Add clk bulk for nop-phy driver.
Signed-off-by: Peng Fan <[email protected]>
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Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the size of states_array to avoid overflow for
dev_pdata->voltages[j] and dev_pdata->states[j].
As the size of array is GPIO_REGULATOR_MAX_STATES, the size of
states_array is limited by GPIO_REGULATOR_MAX_STATES * 2 = 4
instead of 8 previously.
The value of the "count" variable is limited by the third parameter of
fdtdec_get_int_array_count.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This reverts commit 18426bf02217de2e9bb2b41eaa74d769892c55ef.
Signed-off-by: Tom Rini <[email protected]>
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This reverts commit 82e21b391bd315f6fe0e0b79326af8a141e9cca7.
Signed-off-by: Tom Rini <[email protected]>
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The register to enable/disable the write-permission of DBI RO
registers should be accessed via the CFG_ADDR/CFG_DATA registers
instead of accessing directly.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.
Signed-off-by: Razvan Ionut Cirjan <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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Make the MPC8XXX gpio driver to support the fsl-layerscape.
Signed-off-by: hui.song <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more static scenarios such as hardwired PCI endpoints
that get initialized later in the system setup) that would allow
two things:
- for a SRIOV capable PCI EP identified by its B.D.F specify
the maximum number of VFs that will ever be created for it
- for hot-plug case, specify the B.D.F with which the device
will show up on the PCI bus
More details can be found in the included documentation:
arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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- sun8i emac changes (Andre)
- SCP firmware (Samuel)
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add Kconfig option for pcf8563 driver and
run tools/moveconfig.py
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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dev_err has been used for debugging and a few dev_err message are
printed for normal code execution. Make them dev_dbg instead.
Signed-off-by: Fabien Parent <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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By using a hypervisor call, we can implement DEBUG_UART on xen.
This will allow us to see messages even earlier than serial_init().
Signed-off-by: AKASHI Takahiro <[email protected]>
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At present, DM_FLAG_PRE_RELOC is set only if !OF_CONTROL.
It doesn't make sense for this para-virtualized driver.
With this patch applied, you will be able to see early boot messages:
U-Boot 2020.10-00001-ge442e71a6c52-dirty (Oct 15 2020 - 11:02:25 +0900)
xenguest
Xen virtual CPU
Model: XENVM-4.15
DRAM: 128 MiB
PVBLOCK:
(XEN) gnttab_mark_dirty not implemented yet
pvblock: 0
In: hypervisor
Out: hypervisor
Err: hypervisor
xenguest#
Signed-off-by: AKASHI Takahiro <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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1. Rename AST2500 reset driver from ast2500-reset.c
to reset-ast2500.c
2. Rename AST2500 reset kconfig option from AST2500_RESET
to RESET_AST2500
Signed-off-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
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The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.
This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.
The Kconfig description is also updated accordingly.
Signed-off-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
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The 12d152620d commit fixed the get_rate helper because the set_parent
one did not re-parent the clock device to the new parent. The 4d139f3838
commit allows you to remove this workaround by calling the
clk_get_parent_rate routine.
Signed-off-by: Dario Binacchi <[email protected]>
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%s/occured/occurred/
Signed-off-by: Naoki Hayama <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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%s/occured/occurred/
Signed-off-by: Naoki Hayama <[email protected]>
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Add support for the hardware pseudo random number generator found in Qualcomm SoC-s.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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This adds the driver for the IPQ40xx built-in MDIO.
This will be needed to support future PHY driver.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s.
Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW.
FIFO and Block modes are supported, no support for DMA mode is planned.
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Luka Kovacic <[email protected]>
Cc: Luka Perkov <[email protected]>
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No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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