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Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-utmi driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-master driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add sam9x60-pll driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add clk-main driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).
Signed-off-by: Claudiu Beznea <[email protected]>
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Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add helper for clock drivers. These will be used by following
commits in the process of switching AT91 clock drivers to CCF.
Signed-off-by: Claudiu Beznea <[email protected]>
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clk_get_by_indexed_prop() retrieves a clock with dev member being set
with the pointer to the udevice for the clock controller driver. But
in case of CCF each clock driver has set in dev member the reference
to its parent (the root of the clock tree is a fixed clock, every
node in clock tree is a clock registered with clk_register()). In this
case the subsequent operations like dev_get_clk_ptr() on clocks
retrieved by clk_get_by_indexed_prop() will fail. For this, get the
pointer to the proper clock registered (with clk_register()) using
clk_get_by_id() before proceeding.
Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)")
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Do not disable clock if it is a critical one.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Clock re-parenting is not binding the clock's device to its new
parent device, it only calls the clock's ops->set_parent() API. The
changes in this commit re-parent the clock device to its new parent
so that subsequent operations like clk_get_parent() to point to the
proper parent.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In common clock framework the relation b/w parent and child clocks is
determined based on the udevice parent/child information. A clock
parent could be changed based on devices needs. In case this is happen
the functionalities for clock who's parent is changed are broken. Add
a function that reparent a device. This will be used in clk-uclass.c
to reparent a clock device.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Check hw and hw->dev before dereference it.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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- Add error tracing messages to the generic PHY infrastructure
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Merge in v2020.10-rc5
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https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5 (2)
The following bugs are fixed:
* incorrect online help for setenv and env
* description of function efi_mem_carve_out()
* replace printf() by log_err() in stm32mp1_rng driver
A unit test is provided to check that the boot hart id is provided in the
RISC-V device-tree.
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The logging system provides flexible filtering and enhanced output.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Sughosh Ganu <[email protected]>
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Lot of Qualcomm SoC-s use DWC3 controller for both USB2.0 and USB3.0
ports.
Qualcomm has some custom config registers on top of the generic ones,
but for host mode these are not needed.
So lets add the neccessary compatible string.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs.
The driver sets up HS and SS phys.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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There is already existing driver for SMEM so lets enable it for IPQ40xx as well.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo <[email protected]>
Signed-off-by: Haibo Chen <[email protected]>
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add DM/DTS support for the UEC ethernet on QUICC Engine
Block.
Signed-off-by: Heiko Schocher <[email protected]>
Patch-cc: Mario Six <[email protected]>
Patch-cc: Qiang Zhao <[email protected]>
Patch-cc: Holger Brunck <[email protected]>
Patch-cc: Madalin Bucur <[email protected]>
Series-changes: 3
- revert:
commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled")
as now qe works with DM and DM_ETH support.
- fix mailaddress from Holger
Series-changes: 2
- add comments from Qiang Zhao:
- add device node documentation
- I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c
because using drivers/net/fsl_mdio.c leads in none existent
udevice mdio@3320
instead boards with DM ETH support should use now this
driver.
- remove RFC tag
Commit-notes:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This Code should be removed if all boards are converted
to DM/DTS.
- add the DM based qe uec driver under drivers/net/qe
- Therefore copied the files uccf.c uccf.h uec.h from
drivers/qe. So there are a lot of Codingstyle problems
currently. I fix them in next version if this RFC
patch is OK or it needs some changes.
- The dm based driver code is now under drivers/net/qe/dm_qe_uec.c
Used a lot of functions from drivers/qe/uec.c
- seperated the PHY specific code into seperate file
drivers/net/qe/dm_qe_uec_phy.c
END
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add DM support for parallel I/O ports on QUICC Engine Block
Signed-off-by: Heiko Schocher <[email protected]>
Patch-cc: Mario Six <[email protected]>
Patch-cc: Qiang Zhao <[email protected]>
Patch-cc: Holger Brunck <[email protected]>
Series-changes: 2
- remove RFC
- fixed Codingstyle errors, therefore new patch
powerpc, mpc83xx: fix codingstyle issues for qe_io.c
- moved DM part to drivers/pinctrl
Commit-notes:
Open questions / discussion:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This should be removed if all boards are converted to
DM/DTS.
- Unfortunately linux DTS does not use "pinctrl-"
properties, instead "pio-handle" properties.
Even worser old U-Boot code initializes all pins
defined in "const qe_iop_conf_t qe_iop_conf_tab[]"
table in board code. As linux does the same I decided
to also scan through all subnodes containing "pio-map"
property and initialize them too.
The proper solution would be to check for "pio-handle"
when a device is probed.
END
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fix Codingstyle for files in drivers/qe, remaining following
check warnings:
$ ./scripts/checkpatch.pl -f drivers/qe/uec.h
CHECK: Macro argument reuse '_bd' - possible side-effects?
+#define BD_ADVANCE(_bd, _status, _base) \
+ (((_status) & BD_WRAP) ? (_bd) = \
+ ((struct buffer_descriptor *)(_base)) : ++(_bd))
total: 0 errors, 0 warnings, 1 checks, 692 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.h
total: 0 errors, 0 warnings, 0 checks, 214 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uccf.c
total: 0 errors, 0 warnings, 0 checks, 507 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec.c
total: 0 errors, 0 warnings, 0 checks, 1434 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.c
total: 0 errors, 0 warnings, 0 checks, 927 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/qe.c
CHECK: Lines should not end with a '('
+U_BOOT_CMD(
total: 0 errors, 0 warnings, 1 checks, 830 lines checked
Signed-off-by: Heiko Schocher <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
- Hyperflash boot for J7200
- Update Main R5FSS lockstep mode
- R5F remoteproc support for J7200
- Minor env fixes
- Add SPI boot support for am335x-icev2
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Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.
Signed-off-by: Faiz Abbas <[email protected]>
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Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.
Signed-off-by: Faiz Abbas <[email protected]>
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There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.
Signed-off-by: Faiz Abbas <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.
The revised IP has the following two new features:
1. TCMs are auto-initialized during module power-up, and the behavior
is programmable through a MMR bit controlled by System Firmware.
2. The LockStep-mode allows the Core1 TCMs to be combined with the
Core0 TCMs effectively doubling the amount of TCMs available.
The LockStep-mode on previous SoCs could only use the Core0 TCMs.
This combined TCMs appear contiguous at the respective Core0 TCM
addresses.
Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.
Signed-off-by: Suman Anna <[email protected]>
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Use mmc_of_parse() to set the common host properties. That includes
"bus-width", so parsing it can be removed from the driver.
But more importantly, "non-removable" is now respected, which fixes
the usage of eMMC.
Signed-off-by: Andre Heider <[email protected]>
Reviewed-by: Konstantin Porotchkin <[email protected]>
Tested-by: Marek Behún <[email protected]>
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Since the introduction of 'get_cd' callback in sdhci core,
dragonboard410c's MMC interface is broken. It turns out that 'get_cd'
callback checks for the host_caps for validating the chip select. And
since the msm_sdhci driver is not parsing the host_caps from DT, not
all of the cababilities are parsed properly. This results in the MMC
interfaces to be broken.
Hence, fix this by adding a call to 'mmc_of_parse' during driver probe.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Tested-by: Aníbal Limón <[email protected]>
Reviewed-By: Ramon Fried <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Nand writes should skip the bad blocks with "nand write" command.
In case of bad blocks with above 32-bit address, nand_block_isbad()
returns false due to truncated bad block address.
In below code segment,
if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1)))
offset is 64-bit and mtd->erasesize is 32-bit, hence the truncation is
happening. Cast 'mtd->erasesize' with loff_t to fix this issue.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.
Signed-off-by: Chuanjia Liu <[email protected]>
Tested-by: Frank Wunderlich <[email protected]>
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On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.
Signed-off-by: Chuanjia Liu <[email protected]>
Tested-by: Frank Wunderlich <[email protected]>
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v2: modify title description aspeed:clock -> clock:aspeed
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen <[email protected]>
Reviewed-by: Chia-Wei, Wang <[email protected]>
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Rename the ast2500-scu.h to aspeed-clock.h.
Signed-off-by: Ryan Chen <[email protected]>
Reviewed-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
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The commit 57805f2270c4 ("net: bcmgenet: Don't set ID_MODE_DIS when
not using RGMII") needed to be extended for the case of using the
rgmii-rxid. The latest version of the Rasbperry Pi4 dtb files for the
5.4 now specify the rgmii-rxid.
Signed-off-by: Jason Wessel <[email protected]>
Tested-by: Petr Tesarik <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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This commit fixes a serious issue occurring when several network
commands are run on a raspberry pi 4 board: for instance a "dhcp"
command and then one or several "tftp" commands. In this case,
packet recv callbacks were called several times on the same packets,
and send function was failing most of the time.
note: if the boot procedure is made of a single network
command, the issue is not visible.
The issue is related to management of the packet ring buffers
(producer / consumer) and DMA.
Each time a packet is received, the ethernet device stores it
in the buffer and increments an index called RDMA_PROD_INDEX.
Each time the driver outputs a received packet, it increments
another index called RDMA_CONS_INDEX.
Between each pair of network commands, as part of the driver
'start' function, previous code tried to reset both RDMA_CONS_INDEX
and RDMA_PROD_INDEX to 0. But RDMA_PROD_INDEX cannot be written from
driver side, thus its value was actually not updated, and only
RDMA_CONS_INDEX was reset to 0. This was resulting in a major
synchronization issue between the driver and the device. Most
visible behavior was that the driver seemed to receive again the
packets from the previous commands (e.g. DHCP response packets
"received" again when performing the first TFTP command).
This fix consists in setting RDMA_CONS_INDEX to the same
value as RDMA_PROD_INDEX, when resetting the driver.
The same kind of fix was needed on the TX side, and a few variables
had to be reset accordingly (c_index, tx_index, rx_index).
The rx_index and tx_index have only 256 entries so the bottom 8 bits
must be masked off.
Originated-by: Etienne Dublé <[email protected]>
Signed-off-by: Jason Wessel <[email protected]>
Tested-by: Petr Tesarik <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
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As the error message is now displayed by generic phy functions,
the dev_err/pr_err can be change to dev_dbg/pr_debug.
Signed-off-by: Patrick Delaunay <[email protected]>
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As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.
Signed-off-by: Patrick Delaunay <[email protected]>
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As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.
Signed-off-by: Patrick Delaunay <[email protected]>
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As the error message is now displayed by generic phy functions,
the dev_err can be change to dev_dbg.
Signed-off-by: Patrick Delaunay <[email protected]>
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Add an error trace for PHY errors directly in generic phy
functions provided by PHY uclass.
Signed-off-by: Patrick Delaunay <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next
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- This patch moves sata phy powerup from dedicate phy to compphy
and adds invert option for sata powerup routine.
Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90
Signed-off-by: zachary <[email protected]>
Signed-off-by: Ken Ma <[email protected]>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53601
Reviewed-by: Igal Liberman <[email protected]>
Tested-by: Igal Liberman <[email protected]>
[a.heider: adapt to mainline]
Signed-off-by: Andre Heider <[email protected]>
Tested-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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- Mostly DFU fixes and r8152 fixes
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- SH serial bugfix
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The size returned by 'getvar partition-size' should be in bytes, not in
blocks as fastboot uses that value to generate empty partition when
running format [1].
Note that the function was already returning the proper size in bytes
for NAND devices (see struct part_info details).
[1]
https://android.googlesource.com/platform/system/core/+/refs/heads/android10-release/fastboot/fastboot.cpp#1500
Signed-off-by: Gary Bisson <[email protected]>
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