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This patch prevents an issue where the RX packet might have been
accessed by the CPU, which now has cached data from the packet in
the caches and possibly various write buffers, and these data may
be evicted from the caches into the DRAM while the buffer is also
written by the DMA.
By invalidating the buffer after the CPU accessed it and before the
DMA populates the buffer, it is assured that the buffer will not be
corrupted.
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Stephen Warren <[email protected]>
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The current code polls the RX desciptor ring for new packets by reading
the RX descriptor status. This works by accident, as the RX descriptors
are often in non-cacheable memory. However, the driver does support use
of RX descriptors in cacheable memory.
This patch adds a missing RX descriptor invalidation, which assures the
CPU will read a fresh copy of the RX descriptor instead of a cached one.
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Stephen Warren <[email protected]>
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Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Stephen Warren <[email protected]>
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This code programs the next descriptor in the TX descriptor ring into
the hardware as the last valid TX descriptor. The problem is that if
the currenty descriptor is the last one in the array, the code will
not wrap around correctly and use TX descriptor 0 again, but instead
will use TX descriptor at address right past the TX descriptor ring,
which is the first descriptor in the RX ring.
Fix this by adding the necessary wrap-around.
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Stephen Warren <[email protected]>
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The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the field. This could lead to a residual dirty bits being left in
the field 3 from previous transfer, and it generally does. Fully set the
field 3 instead to clear those residual dirty bits.
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Stephen Warren <[email protected]>
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Replace the adhoc debugging ifdeffery with debug_cond() and an
internal SROM_DEBUG macro to select the debug level.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Move the functions in the driver around to better fit future DM
conversion, drop function forward declarations. No functional
change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Rename these functions to dc2114x_{inl,outl}(), use u32 values in
them instead of plain signed integers as all those values are in
fact register values and the driver code does bitwise operations
on them. No functional change intended.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Replace these macros with static functions to permit the compiler to
do type checking on the functions. The INL()/OUTL() functions have to
be moved in this patch as well, as those DE4X5 macros are using them.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Clean up the remaining driver code, macro space alignment, function
declaration indent, replace __attribute__((aligned(32))) with plain
__aligned(32). No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Clean up the SROM accessors to bring them up to standards with
U-Boot coding style. Sort variable into reverse xmas tree. No
functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Clean up the send_setup_frame() to bring it up to standards with
U-Boot coding style, invert the loops where applicable to cut
down the level of indent. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Clean up the driver halt code to bring it up to standards with
U-Boot coding style. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Clean up the driver recv code to bring it up to standards with
U-Boot coding style. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Clean up the driver send code to bring it up to standards with
U-Boot coding style, invert the loops where applicable to cut
down the level of indent. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Clean up the driver init code to bring it up to standards with
U-Boot coding style, no functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Replace the PCI IO access with PCI memory access, the card
supports both, but the former does not work with QEMU SH4.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Replace mips-specific UNCACHED_SDRAM() macro with standard
map_physmem(), which permits the driver to work on other
systems than mips.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Joe Hershberger <[email protected]>
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These macros are not used by any board, remove them to simplify
the driver. The EEPROM accessors are still retained however, as
those might still be useful.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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These macros guard one switch-case statement, which grows mips malta
by some 20 bytes if debug is enabled, and even less if it is not. To
make the code simpler, just support all the NICs and be done with it.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have HCLK_SD assigned-clocks which are usually required for
Linux and don't require to handle them in U-Boot.
assigned-clocks = <&cru HCLK_SD>;
So, mark them as empty in clock otherwise device probe on
those SD controllers would fail.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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- distro boot support for SPI flash
- sifive spi flash driver
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The guessed reason is that the existing logic of filling
tx fifo with data, rx fifo with NULL for tx transfer and
filling rx fifo with data, tx fifo with NULL for rx transfer
is not clear enough to support the Quad Page Program.
SiFive SPI controllers have specific sets of watermark
registers and SPI I/O directions bits in order to program
SPI controllers clear enough to support all sets of operating
modes.
Here is the exact programing sequence that would follow on this
patch and tested via SPI-NOR and MMC_SPI.
- set the frame format proto, endian
- set the frame format dir, set it for tx and clear it for rx
- TX transfer:
fill tx fifo with data.
wait for TX watermark bit to clear.
- RX transfer:
fill tx fifo with 0xff.
write nbytes to rx watermark register
wait for rx watermark bit to clear.
read the rx fifo data.
So, this patch adopts this program sequence and fixes the existing
I/O direction bit.
Cc: Vignesh R <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Tested-by: Sagar Kadam <[email protected]>
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SiFive SPI controller has a proto bit field in frame format
register which would be used to configure the SPI I/O protocol
lines used on specific transfer.
Right now the driver is configuring this proto using slave->mode,
for all types of transctions. This makes the driver unable to
function since the proto needs to configure dynamically for
each and every transaction separately at runtime.
Now, the controller driver supports per transfer via spi-mem
exec_opo, so add the fmt_proto flag and fill the per transfer
buswidth so that the controller configures the proto bit at
runtime.
This patch fixes the SPI controller works with SPI NOR flash
on quad read with page program.
Cc: Vignesh R <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Tested-by: Sagar Kadam <[email protected]>
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SiFive SPI controller is responsible to handle the
slave devices like mmc spi and spi nor flash.
The controller is designed such a way that it would
handle the slave transactions based on the I/O protocol
numbers, example if spi nor slave send quad write opcode
it has to send alone with I/O protocol number of 4 and
if it try to send data it has to send I/O protocol number
along with 4 line data.
But the current spi-xfer code from spi-mem is combining
the opcode and address in a single transaction, so the
SPI controller will be unable to identify the I/O protocol
number of opcode vs address.
So, add the spi-mem exec_op with spi-xfer of opcode, address
and data as a separate transaction. This doesn't remove
the .xfer of dm_spi_ops since mmc spi will make use of it.
Note: This code might have moved to the spi-mem core area
once we have done the dedicated tests on other controllers
and have real reason to move.
Cc: Vignesh R <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Tested-by: Sagar Kadam <[email protected]>
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Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on
various platforms as former is not present. Add the entry.
Linux already has both the flashes present. A snippet below:
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...},
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...},
Signed-off-by: Kuldeep Singh <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Enable designware watchdog driver for rk3399 if WDT defined.
Cc: Marek Vasut <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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IS25WP256 flash chips do support 4byte address opcodes,
so enable support for it.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Sagar Kadam <[email protected]>
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Enable QE bit for ISSI flash chips.
QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.
Cc: Sagar Shrikant Kadam <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Usually variable name slave is used for spi_slave structure
and slave_plat for the dm_spi_slave_platdata.
Let's follow this meaningful notation by replacing slave
with slave_plat for dm_spi_slave_platdata structure.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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- DM ACPI support (Part A)
- Improve support for chain-loading x86 U-Boot
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2020.07-rc2
mmc:
- Fix dt property handling via generic function
clk:
- Fix versal watchdog clock setting
nand:
- Fix zynq nand command comparison
xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose
zynq:
- Kconfig alignments
- Fix nand cse configuration
zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates
Signed-off-by: Tom Rini <[email protected]>
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- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
platforms.
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When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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A device may want to write out ACPI tables to describe itself to Linux.
Add a method to permit this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
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Probe the FMan MACs based on the device tree while
retaining the legacy code/functionality.
One notable change introduced here is that, for DM_ETH,
the name of the interfaces is corrected to the fmX-macY
format, that avoids the referral to the MAC block names
which were incorrect for FMan v3 devices (i.e. DTSEC,
TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1).
The legacy code is left unchanged in this respect.
Signed-off-by: Madalin Bucur <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Allow the MDIO devices to be probed based on the device tree.
Signed-off-by: Madalin Bucur <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Move the receive buffer free code in a separate function.
Signed-off-by: Madalin Bucur <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Change the init_phy() parameter to simplify the code.
Signed-off-by: Madalin Bucur <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Make any adjustments necessary in order to support DPAA2 devices probed
using CONFIG_DM_ETH. While at it, fixup some styling issues aroung the
switch-case statement.
Signed-off-by: Ioana Ciornei <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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When CONFIG_DM_ETH is enabled DPAA2 network interfaces will now probe
based on DTS nodes with the "fsl,qoriq-mc-dpmac" compatible.
In this case, transform the ldpaa_eth driver into a UCLASS_ETH driver
and reuse the _open()/_tx()/_stop() functions already inplemented.
For the moment, the ldpaa_eth driver will support both configurations:
with or without CONFIG_DM_ETH enabled. Any 'struct eth_device' occurrence
now has a matching 'struct udevice' made mutually exclusive based on the
state of CONFIG_DM_ETH.
Signed-off-by: Florin Laurentiu Chiculita <[email protected]>
Signed-off-by: Ioana Ciornei <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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Add a driver for the MDIO interface integrated in the mEMAC (Multi-rate
Ethernet Media Access Controller) and the Fman 10G Ethernet MACs.
Signed-off-by: Ioana Ciornei <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Add a driver for the rng device found on rockchip platforms.
Support rng module of crypto v1 and crypto v2.
Signed-off-by: Lin Jinhan <[email protected]>
Tested-by: Peter Robinson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Commit: 0ebb261a0b2d ("spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum")
in linux.
When defining spi_mem_op templates we don't necessarily know the size
that will be passed when the template is actually used, and basing the
supports_op() check on op->data.nbytes to know whether there will be
data transferred for a specific operation is not possible.
Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum so that we can base
our checks on op->data.dir instead of op->data.nbytes.
This also fixes a bug identified with the atmel-quaspi driver.
The spi-nor core, when erasing sectors, fills the spi_mem_op template
using SPI_MEM_OP_NO_DATA, which initializes all the data members with
value zero. This is wrong because data.dir is treated as SPI_MEM_DATA_IN,
which translates in our driver to read accesses for erases (RICR), while
the controller expects write accesses (WICR).
Signed-off-by: Tudor Ambarus <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Toshiba recently launched new revisions of their serial SLC NAND series.
TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements.
Basic parameters are same so lets add support for this new revision.
Datasheet: https://business.kioxia.com/info/docget.jsp?did=58601&prodName=TC58CVG2S0HRAIJ
Signed-off-by: Robert Marko <[email protected]>
Tested-by: Luka Kovacic <[email protected]>
Cc: Luka Perkov <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Linux has good support for Toshiba SPI-NAND, so lets import it.
Signed-off-by: Robert Marko <[email protected]>
Tested-by: Luka Kovacic <[email protected]>
Cc: Luka Perkov <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The s25fl256s0 supports dual and quad read like s25fl256s1.
Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ
flags to the flash_info entry.
Tested on real silicon and confirmed to be working.
Signed-off-by: Bacem Daassi <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Commit 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support")
enables octal mode(1-1-8) support in spi-nor framework.
mt35xu512aba and mt35xu02g supports SINGLE and OCTAL I/O. Hence, enable
SPI_NOR_OCTAL_READ flag for these flashes.
Signed-off-by: Kuldeep Singh <[email protected]>
Reviewed-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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"assigned-clock-parents" and "assigned-clock-rates" DT properties take
effect only after ofdata_to_platdata() when clk_set_defaults() is called
in device_probe(). Therefore clk get rate() would return a wrong value
in ofdata_to_platdata() when compared with probe. Hence it needs to be
moved to probe.
Tested on u-boot-ti/next.
Signed-off-by: Pratyush Yadav <[email protected]>
Acked-by: Vignesh Raghavendra <[email protected]>
Acked-by: Simon Goldschmidt <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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hweight32 is a somewhat expensive way to check for power-of-2. Use the
is_power_of_2 helper, which does the standard and cheap idiom
foo&(foo-1)==0.
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-96 (-96)
Function old new delta
spi_nor_write 388 292 -96
Signed-off-by: Rasmus Villemoes <[email protected]>
Acked-by: Vignesh Raghavendra <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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