| Age | Commit message (Collapse) | Author |
|
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <[email protected]>
|
|
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <[email protected]>
|
|
Add i.MX8MP clk driver for i.MX8MP CLK driver model usage
Signed-off-by: Peng Fan <[email protected]>
|
|
Add imx_clk_mux2_flags which will be used by i.MX8MP
Signed-off-by: Peng Fan <[email protected]>
|
|
PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.
Signed-off-by: Robin Gong <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <[email protected]>
|
|
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Add i.MX8MP compatible to let the pinctrl driver could support
i.MX8MP.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:
When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().
The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:
- The power-on-reset value of SCCR[PCICM] is 0, so
mpc83xx_clk_enable() would probably need to be tought to enable the
clock.
- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
depending on the CFG_CLKIN_DIV configuration input, but that can't
be read from software, so to properly fill out
->speed[MPC83XX_CLK_PCI] I think one would need guidance from
Kconfig or dtb.
Partially fixes: 07d538d281 clk: Add MPC83xx clock driver
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Mario Six <[email protected]>
|
|
This adds a message to lists_bind_fdt when it skips initializing a device
pre-relocation. I've had a couple errors where a device didn't initialize
properly because one of its dependencies was missing.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Since the ofdata_to_platdata() method can allocate resources, add it as a
new devres phase.
Signed-off-by: Simon Glass <[email protected]>
|
|
At present we only support two phases where devres can be used:
bind and probe. This is handled with a boolean. We want to add a new
phase (platdata), so change this to an enum.
Signed-off-by: Simon Glass <[email protected]>
|
|
The devres functionality has very few users in U-Boot, but it still should
have tests. Add a few basic tests of the main functions.
Signed-off-by: Simon Glass <[email protected]>
|
|
At present when CONFIG_DEBUG_DEVRES is enabled, U-Boot prints log messages
to the console with every devres allocation/free event. This causes most
tests to fail since the console output is not as expected.
In particular this prevents us from adding a device to sandbox which uses
devres in its bind method.
Move devres over to use U-Boot's logging feature instead, and add a new
category for devres.
Signed-off-by: Simon Glass <[email protected]>
|
|
We want to avoid allocating platform data twice. This could happen if
device_probe() is called after device_ofdata_to_platdata() for the same
device.
Add a flag to track whether device_ofdata_to_platdata() has been called on
a device. Check the flag to make sure it doesn't happen twice, and clear
the flag when the data is freed.
Signed-off-by: Simon Glass <[email protected]>
|
|
Add a new internal function, device_ofdata_to_platdata() to handle
allocating private space associated with each device and reading the
platform data from the device tree.
Call this new function from device_probe().
Signed-off-by: Simon Glass <[email protected]>
|
|
At present the parent is probed before the child's ofdata_to_platdata()
method is called. Adjust the logic slightly so that probing parents is
not done until afterwards.
Signed-off-by: Simon Glass <[email protected]>
|
|
This method is supposed to extract platform data from the device tree. It
should be done before the device itself is probed. Move it earlier in the
device_probe() function.
Signed-off-by: Simon Glass <[email protected]>
|
|
Remove this duplicated code, since the 'fail' label does this immediately.
Signed-off-by: Simon Glass <[email protected]>
|
|
At present the clock driver reads its ofdata in the probe() method. This
is not correct although it is often harmless.
However in this case it causes a problem, something like this:
- ast_get_scu() is called (from somewhere) to get the SCI address
- this probes the clock
- first sets up ofdata (which does nothing at present)
- DM marks clock device as active
- DM calls pinctrl
- pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
- ast_get_scu() probes the clock, but sees it already marked as
probed
- ast_get_scu() accesses the clock's private data, with scu as NULL
- DM calls clock probe function ast2500_clk_probe() which reads scu
By putting the read of scu into the correct method, scu is read as part of
ofdata setup, and everything is OK.
Note: This problem did not matter until now since DM always probed all
parents before reading a child's ofdata. The fact that pinctrl is a child
of clock seems to trigger this strange bug.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
|
|
It is not possible to access a device on a PCI bus that has not yet been
probed, since the bus number is not known. Add a warning to catch this
error.
Signed-off-by: Simon Glass <[email protected]>
|
|
These macros use __FILE__ which inserts the full path of the object file
into U-Boot, thus increasing file size. Drop these usages.
An older version of this patch was submitted here:
http://patchwork.ozlabs.org/patch/1205784/
Signed-off-by: Simon Glass <[email protected]>
|
|
Use this macros instead of the linux ones, as the output is smaller.
Signed-off-by: Simon Glass <[email protected]>
|
|
Add a driver for the virtio-rng device on the qemu platform. The
device uses pci as a transport medium. The driver can be enabled with
the following configs
CONFIG_VIRTIO
CONFIG_DM_RNG
CONFIG_VIRTIO_PCI
CONFIG_VIRTIO_RNG
Signed-off-by: Sughosh Ganu <[email protected]>
|
|
Add a sandbox driver for random number generation. Mostly aimed at
providing a unit test for rng uclass.
Signed-off-by: Sughosh Ganu <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Add a driver for the rng device found on stm32mp1 platforms. The
driver provides a routine for reading the random number seed from the
hardware device.
Signed-off-by: Sughosh Ganu <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Acked-by: Patrick Delaunay <[email protected]>
Remove a superfluous blank line
Signed-off-by: Heinrich Schuchardt <[email protected]>
|
|
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.
Signed-off-by: Sughosh Ganu <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Acked-by: Patrick Delaunay <[email protected]>
|
|
Add a uclass for reading a random number seed from a random number
generator device.
Signed-off-by: Sughosh Ganu <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
off-on-delay-us has been supported by Linux, so let's use it.
Signed-off-by: Peng Fan <[email protected]>
|
|
Load the optional resource table from the firmware, and write its
address in the dedicated backup register.
Signed-off-by: Fabien Dessenne <[email protected]>
Acked-by: Patrick Delaunay <[email protected]>
|
|
Update the dedicated backup register to track the coprocessor state and
rely on that register to compute the .is_running() value (which expects
a return value of 0 -not 1- if the processor is running).
Signed-off-by: Fabien Dessenne <[email protected]>
Acked-by: Patrick Delaunay <[email protected]>
|
|
Add rproc_elf_load_rsc_table(), which searches for a resource table in
an elf64/elf32 image, and if found, copies it to device memory.
Add also the elf32 and elf64 variants of this API.
Add a test for this.
Signed-off-by: Fabien Dessenne <[email protected]>
Acked-by: Patrick Delaunay <[email protected]>
Reviewed-by: Lokesh Vutla <[email protected]>
|
|
This function will be used by the SPL to get the names of images to load
from the FIT. This allows to load different images based on runtime HW
detection.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Make the board driver available in the SPL too. The board driver is a way
to provide useful information about the board and that can be useful in
the SPL too.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx
New for 2020.04
---------------
- New boards
Embedded Artists COM board
Xea Board
- Switch to DM:
Aristainetos boards
Toradex colibri (DM_ETH)
iCubox
GE bx50v3
mx7dsabre (DM_ETH)
cx9020
- New features:
Bootaux with elf files
Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
DHCOM i.MX6 PDK
Engicam
i.MX8M tools (imx8m_image)
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2020.04 cycle
This feature set is a patch series from Tudor Ambarus which includes
parsing of the spi flash SFDP parser for SST flashes, and using those
tables to retrieve unique saved per device MAC address. This is then
used as base mac address on the SAMA5D2 Wireless SOM EK board.
|
|
The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.
The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.
Signed-off-by: Thor Thayer <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
|
|
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.
Signed-off-by: Thor Thayer <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
|
|
Add SDRAM driver for Agilex SoC.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.
Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.
agilex-clock.h is from Linux commit ID cd2e1ad12247.
Signed-off-by: Chee Hong Ang <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.
SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
Add an option for building cache drivers in SPL.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
|
|
When the `dfu` command is called from the U-Boot environment,
it now accepts an optional parameter that specifies a timeout (in seconds).
If a DFU connection is not made within that time the `dfu` command exits
(as it would if Ctrl+C was pressed). If the timeout is left empty or being
zero the `dfu` command behaves as it does now.
This is useful for allowing U-Boot to check to see if anything wants to
upload new firmware before continuing to boot.
The patch is based on the commit
https://github.com/01org/edison-u-boot/commit/5e966ccc3c65c18c9783741fa04e0c45e021780c
by Sebastien Colleur, which has been heavily reworked due to U-Boot changes
in the past.
Signed-off-by: Brad Campbell <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
|
|
These files should not be included in meson header files. Drop them and
tidy up the affected C files.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Anatolij Gustschin <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
|