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According to the R-Car Gen3 Hardware Manual Rev 1.50, the MOD_SEL0
bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are
selected.
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR /
MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was
confirmed in the R-Car Gen3 Hardware Manual Rev.1.50.
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22]
of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795
/ r8a7796 / r8a77965. This information was confirmed in the R-Car
Gen3 Hardware Manual Rev.1.50.
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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This patch fixes to the correct names, and "_" is not include after
"adg" for r8a7795/r8a7796/r8a77965. This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03",
and "HDMI0_CEC" to "GP7_02". This information was confirmed in the
R-Car Gen3 Hardware Manual Rev.1.50.
Signed-off-by: Hiroyuki Yokoyama <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Moves below DDR specific defines to Kconfig:
CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH
Signed-off-by: Rajesh Bhagat <[email protected]>
Reviewed-by: York Sun <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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- SoCFPGA cache/gpio fixes
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- Gen2/Gen3 fixes for warnings and sdhi
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_omap3_spi_set_wordlen() indexed the regs->channel[] array with the
old wordlen (instead of the chipselect number) when reading the current
CHCONF register value. This meant it read from the wrong memory location,
modified that value, and then wrote it back to the correct CHCONF
register. The end result is that most slave configuration settings would
be lost, such as clock divisor, clock/chipselect polarities, etc.
Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model")
Signed-off-by: David Rivshin <[email protected]>
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Currently, timer driver is bound only for hart0.
There is no mandatory requirement that hart0 should always
come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
in S-mode because it only has M-mode.
The timer driver should be bound for boot hart.
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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It is possible that input clock is not available because clk
device was not available and 'clock-frequency' DT property is
also not available.
In this case, instead of failing we should just skip baudrate
config by returning zero.
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
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Compute the baud rate multipler with more precision.
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
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This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra <[email protected]>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux
Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
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Fix MID bit field check to correctly identify all GEM hardwares.
The check is updated as per macb driver in Linux location:
<linux_sources>/drivers/net/ethernet/cadence/macb_main.c:259
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
Reviewed-by: Lukas Auer <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Don't fail in macb_enable_clk() if clk_enable() returns
-ENOSYS because we get -ENOSYS for fixed-rate clocks.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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According to latest specification rev.0026 and after confirmation with
HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on
H3 ES2.0 SoC. Make it so.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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According to latest specification rev.0026, when HOST_MODE bit 0
(WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear
HOST_MODE bit 8 in such case and align the code with Linux and
avoid possible unforeseen issues.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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gpio_get_value should return 0 or 1, not the value of bit & (1 << pin)
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Julien Beraud <[email protected]>
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- Add support for sound.
Albeit the big changeset, changes are pretty limited to x86 only and a
few new sound drivers used by x86 so I think it would be good to have
this in the next release.
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- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs
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Migrate TEGRA_KEYBOARD from headers to Kconfig, only the seaboard uses it but we
drop CONFIG_KEYBOARD as the driver doesn't use the legacy drv_keyboard_init.
Signed-off-by: Peter Robinson <[email protected]>
Cc: Tom Warren <[email protected]>
Cc: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Migrate USB_EHCI_TEGRA from headers to Kconfig
Signed-off-by: Peter Robinson <[email protected]>
Cc: Tom Warren <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Marcel Ziswiler <[email protected]>
Cc: [email protected]
Cc: Lucas Stach <[email protected]>
Cc: Stefan Agner <[email protected]>
Cc: Alban Bedel <[email protected]>
Cc: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Migrate SYS_I2C_TEGRA from headers to Kconfig
Signed-off-by: Peter Robinson <[email protected]>
Cc: Tom Warren <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Marcel Ziswiler <[email protected]>
Cc: [email protected]
Cc: Lucas Stach <[email protected]>
Cc: Stefan Agner <[email protected]>
Cc: Alban Bedel <[email protected]>
Cc: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Enable sound on samus using the broadwell I2S and an RT5677 audio codec.
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Add a sound driver for samus which ties together the audio codec and
I2S controller.
For now broadwell_sound is commented out in the makefile since we cannot
compile it without sound support enabled. The next commit fixes this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This audio codec is used on samus. Add a driver for it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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I2S is used to send digital audio data to an audio codec. Add support for
this on broadwell.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add a sound driver which can output simple beeps using this legacy timer.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add sound support for link, using the HDA codec implementation.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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When testing the sound system we don't need the hear the beeps. The
testing works by checking the data that would be emitted. Add a
device-tree property to silence the sound, and enable it for testing.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The Intel High-definition Audio is a newer-generation audio system which
provides for transfer of a large number of audio stream, each containing
up to 16 channels.
Add support for HDA as a library which can be used by other drivers.
U-Boot currently uses only two channels (stereo).
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Some audio codecs such as Intel HDA do not need to use digital data to
play sounds, but instead have a way to emit beeps. Add this interface as
an option. If the beep interface is not supported, then the sound uclass
falls back to the I2S interface.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This method in the sound API is optional since some drivers can do this
when probing or as part of SoC init. Mark it as such.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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At present the PCH has 4 operations and these are reasonably widely used
in the drivers. But sometimes we want to add rarely used operations, and
each of these currently adds to the size of the PCH operations table.
Add an ioctl() method which can be easily expanded without any more impact
on the operations table.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This uclass currently has no tests. Add a sandbox driver and some simple
tests to provide basic coverage.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: Use "sandbox,pch" for the compatible string, for consistency]
Signed-off-by: Bin Meng <[email protected]>
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At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This function is not used outside this file so make it static.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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At present this driver does not check whether it is able to actually
communicate with the I2C controller. It prints a timeout message but still
considers the probe to be successful.
To fix this, add some checking that the init succeeds.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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At present it is not possible to use the syscon devices for PCI devices
since a regmap is required. Since PCI uses a 3-cell address the conversion
of the 'reg' property to an address always fails. In any case, the regmap
is not useful with PCI since devices are accessed through the PCI bus
which regmap does not support.
Add a special case for PCI syscon devices, so that they don't set up a
regmap.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Before the patch scsi would report the same device number for all SCSI
devices, e.g.
Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Device 0: (1:0) Vendor: ATA Prod.: Rev:
Type: Hard Disk
Capacity: not available
With the patch the same device number is reported as is used in
scsi_read():
Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Device 1: (1:0) Vendor: ATA Prod.: Rev:
Type: Hard Disk
Capacity: not available
Signed-off-by: Heinrich Schuchardt <[email protected]>
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fsl_ddr_board_options is generally defined in board
board's ddr.c, but some boards like lx2160ardb board
does not need this function.
Defining fsl_ddr_board_options as weak function to
resolve compilation errors for such boards.
Signed-off-by: Priyanka Jain <[email protected]>
[PK: Fix checkpatch warnings]
Signed-off-by: Prabhakar Kushwaha <[email protected]>
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- Misc Gen5 fixes
- stratix10 bugfix
- dwmmc bugfix
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This patch prevent the Stratix 10 FPGA driver incorrectly return the
transaction ID as the mailbox error code. It should always return the
actual mailbox error code from SDM firmware.
Signed-off-by: Ang, Chee Hong <[email protected]>
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Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.
Signed-off-by: Ley Foon Tan <[email protected]>
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Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.
This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmidt <[email protected]>
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