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Rockchip RK3576 SoC has two built-in GMACs which connect to external PHYs
via RGMII interface. The RGMII link can be clocked by either the PHY or
the SoC. When the SoC is the master, as is the case on the RK3576 EVB1,
the output clock needs to be configured in the CRU.
Add the respective logic for getting and setting the RGMII reference clock
output for both GMAC0 and GMAC1.
Signed-off-by: Alexey Charkov <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Decode the CPU part number from PART_NUM fuse and print it in CPU name.
For iMX95 and iMX952 Part number fuse is defined as:
[7:6] : Package description
[5:2] : Segment
[1:0] : Number of A55 cores
For iMX94, the PART_NUM[7:0] fuse directly reflects the
part number value.
Signed-off-by: Ye Li <[email protected]>
Acked-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add support for the on-die Thermal Monitoring Unit (TMU) of the
new QorIQ/Layerscape SoCs (LX2160A, LS1028A, LS1088A, ...):
examples on a lx2160:
=> temperature list
| Device | Driver | Parent
| tmu@1f80000 | imx_tmu | root_driver
| cluster67-thermal | imx_tmu | tmu@1f80000
| ddr1-cluster5-thermal | imx_tmu | tmu@1f80000
| wriop-thermal | imx_tmu | tmu@1f80000
| dce-qbman-hsio2-thermal | imx_tmu | tmu@1f80000
| ccn-dpaa-tbu-thermal | imx_tmu | tmu@1f80000
| cluster4-hsio3-thermal | imx_tmu | tmu@1f80000
| cluster23-thermal | imx_tmu | tmu@1f80000
=> temperature get tmu@1f80000
tmu@1f80000: 82000 mC
=> temperature get wriop-thermal
wriop-thermal: 81000 mC
The parent tmu@... node owns the MMIO and calibration; one
UCLASS_THERMAL device is bound per/thermal-zones site so each shows
up by its zone name:
=> dm tree
...
thermal 2 [ + ] imx_tmu |-- tmu@1f80000
thermal 3 [ + ] imx_tmu | |-- cluster67-thermal
thermal 4 [ + ] imx_tmu | |-- ddr1-cluster5-thermal
thermal 5 [ + ] imx_tmu | |-- wriop-thermal
thermal 6 [ + ] imx_tmu | |-- dce-qbman-hsio2-thermal
thermal 7 [ + ] imx_tmu | |-- ccn-dpaa-tbu-thermal
thermal 8 [ + ] imx_tmu | |-- cluster4-hsio3-thermal
thermal 9 [ + ] imx_tmu | `-- cluster23-thermal
...
The dtsi additions mirror the existing fsl-ls1028a.dtsi: the LX2160A
SoC dtsi gains the tmu@1f80000 node plus a thermal-zones hierarchy
with 7 sites:
cluster67-thermal site 0 A72 clusters 6 + 7
ddr1-cluster5-thermal site 1 DDR1 + A72 cluster 5
wriop-thermal site 2 WRIOP
dce-qbman-hsio2-thermal site 3 DCE + QBMAN + HSIO2
ccn-dpaa-tbu-thermal site 4 CCN508 + DPAA + TBU
cluster4-hsio3-thermal site 5 A72 cluster 4 + HSIO3
cluster23-thermal site 6 A72 clusters 2 + 3
Signed-off-by: Vincent Jardin <[email protected]>
Suggested-by: Tom Rini <[email protected]>
Inspired-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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It is designed as a generic UCLASS_THERMAL driver for any JEDEC
JC-42.4 family of on-DIMM temperature sensors (TSE2004av and
compatible parts).
The driver reads the temperature register over DM I2C.
The "jedec,jc-42.4-temp" compatible is Linux-aligned (see
Documentation/devicetree/bindings/hwmon/jedec,jc-42.4-temp.yaml in
the Linux tree).
When CMD_TEMPERATURE is enabled, the sensor becomes available with
the standard commands "temperature list" / "temperature get".
Signed-off-by: Vincent Jardin <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_find_subnode(dev_ofnode(dev), ...) with
dev_read_subnode(dev, ...).
No functional change.
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_read_u32(dev_ofnode(dev), ...) with
dev_read_u32(dev, ...), ofnode_read_string(dev_ofnode(dev), ...) with
dev_read_string(dev, ...), and ofnode_for_each_subnode(node,
dev_ofnode(dev)) with dev_for_each_subnode(node, dev).
No functional change.
Reviewed-by: Casey Connolly <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_read_string(dev_ofnode(dev), ...) with
dev_read_string(dev, ...).
No functional change.
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_read_u32_index(dev_ofnode(dev), ...) with
dev_read_u32_index(dev, ...).
No functional change.
Reviewed-by: Casey Connolly <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_read_bool(dev_ofnode(dev), ...) with
dev_read_bool(dev, ...).
No functional change.
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_for_each_subnode(subnode, dev_ofnode(dev)) with
dev_for_each_subnode(subnode, dev) and ofnode_read_u32_default(
dev_ofnode(dev), ...) with dev_read_u32_default(dev, ...).
No functional change.
Signed-off-by: Peng Fan <[email protected]>
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Replace the manual ofnode_read_u32() + ofnode_get_by_phandle() sequence
with a single dev_read_phandle_with_args() call to resolve the
amlogic,hhi-sysctrl phandle. This is cleaner and avoids the intermediate
phandle value and ofnode_valid() check.
No functional change.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Replace the manual ofnode_read_u32() + ofnode_get_by_phandle() sequence
with a single dev_read_phandle_with_args() call to resolve the
amlogic,ao-sysctrl phandle. This is cleaner and avoids the intermediate
phandle value and ofnode_valid() check.
No functional change.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Use dev_read_addr_index() which supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.
No functional changes.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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SD initialization failure happens with some UHS-I SD cards on
iMX8MM/iMX93/iMX91 EVK after
commit 4fcba5d556b4 ("regulator: implement basic reference counter").
When sending operation condition to SD card, the OCR does not return
correct status. The root cause is regulator on/off delay is missed
in MMC power cycle with above commit, so SD card is not completely
power off.
When SD startup, the sequence of MMC power cycle is:
mmc_power_init(get vmmc_supply dev) -> mmc_power_off -> udelay(2000)
-> mmc_power_on
Before above commit, as a fixed regulator, the GPIO is set as:
GPIO inactive (in mmc_power_init) ->
GPIO inactive and delay off-on-delay-us (in mmc_power_off) ->
udelay(2000) ->
GPIO active (in mmc_power_on)
After the commit:
GPIO inactive (in mmc_power_init) ->
enable_count is 0, regulator_set_enable returns -EALREADY immediately,
so GPIO is inactive but No off-on-delay-us (in mmc_power_off) ->
udelay(2000) ->
GPIO active (in mmc_power_on)
Move the off-on-delay-us delay before setting GPIO active to fix the issue.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Replace all ofnode_read_*() / ofnode_read_bool() / ofnode_get_property()
calls with their dev_read_*() equivalents across
octeontx_mmc_get_valid(), octeontx_mmc_get_config(),
octeontx_mmc_host_probe() and octeontx_mmc_host_child_pre_probe().
Remove the intermediate 'ofnode node' local variables, the now-unused
'host->node' assignment in the probe function, and the corresponding
'ofnode node' field from struct octeontx_mmc_host.
No functional change.
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_read_u32(), ofnode_get_property() and
ofnode_read_string_index() with their dev_read_*() equivalents in
msm_sdc_clk_init(). Remove the intermediate 'ofnode node' local
variable.
No functional change.
Reviewed-by: Casey Connolly <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Replace ofnode_read_*() calls with their dev_read_*() equivalents in
fsl_esdhc_of_to_plat(). Remove the intermediate 'ofnode node' local
variable and the now-unnecessary <dm/ofnode.h> include.
No functional change.
Signed-off-by: Peng Fan <[email protected]>
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Use dev_read_addr_ptr() which supports both live device tree and flat
DT backends, avoiding direct dependency on devfdt_* helpers.
No functional changes.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Use livetree API which supports both live device tree and flat DT backends,
avoiding direct dependency on devfdt_* helpers.
No functional changes.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Initial regulator mode was read from dts but never applied.
This caused a mismatch between saved mode and actual regulator mode.
Apply the current mode from priv->mode during enable() and move
rpmh_regulator_vrm_set_mode function before rpmh_regulator_set_enable_state().
Signed-off-by: Federico Amedeo Izzo <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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dev_read_addr does not return a void* but fdt_addr_t.
Replace invalid usage of dev_read_addr by dev_read_addr_ptr.
v2:
- Replace dev_read_addr by dev_read_addr_ptr
- Change error to EINVAL
Signed-off-by: Francois Berder <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
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Use dev_remap_addr() to replace devfdt_remap_addr which supports both live
device tree and flat DT backends, avoiding direct dependency on
devfdt_* helpers.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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devfdt_get_addr() returns FDT_ADDR_T_NONE(-1UL) when fail, using
"!priv->regs" to check return value is wrong.
Replace devfdt_read_addr() with dev_read_addr_ptr() when retrieving the
register base address.
dev_read_addr_ptr() supports both live device tree and flat DT backends,
avoiding direct dependency on devfdt_* helpers.
Also use "void __iomem *" to replace "phys_addr_t" to avoid type
casting.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Replace devfdt_read_addr_size_index() with dev_read_addr_size_index() when
retrieving the register base address.
dev_read_addr_size_index() supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The OcteonTX watchdog driver currently matches arm,sbsa-gwdt.
On systems with multiple watchdog devices this can be ambiguous since
arm,sbsa-gwdt is a generic SBSA binding.
Replace the SBSA match with SoC-specific Marvell compatibles
marvell,cn10624-wdt and marvell,cn9670-wdt.
These compatibles align with the upstream Linux device tree binding:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/watchdog/marvell,cn10624-wdt.yaml
Reviewed-by: Aaro Koskinen <[email protected]>
Signed-off-by: Juuso Rinta <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The WOR register is 32 bits, so any tick count exceeding U32_MAX is
truncated by writel(). A large requested timeout can wrap to a small
value causing the watchdog to fire sooner than requested.
Clamp the calculated value to U32_MAX prior to writing the register so
over-large requests will be set to the maximum timeout value.
Found by code review.
Signed-off-by: Juuso Rinta <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Rockchip SoCs typically reset with all (or most) clocks ungated. Because
of this, U-Boot clock drivers for Rockchip typically do not implement
the optional clk-uclass enable/disable ops.
Normal driver model behavior is to return -ENOSYS when an uclass ops
is not implemented.
Ignore -ENOSYS to allow the designware watchdog driver to be probed on
platforms that do not implement the clk-uclass enable/disable ops, e.g.
Rockchip RK3308.
Signed-off-by: Jonas Karlman <[email protected]>
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As exposed by "make randconfig", we have an issue with the dependencies
for WDT_MAX6370. It needs to select both GPIO and DM_GPIO not just
DM_GPIO.
Signed-off-by: Tom Rini <[email protected]>
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Update the orion_wdt.c to support armada-xp and similar SoCs. The WDT
block used in armada-xp is fairly close to the armada-380 with just a
few differences that can be handled based on the compatible property.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The original PolarFire SoC mailbox devicetree bindings described the
control/status and interrupt registers as standalone reg regions of the
mailbox device. This was incorrect, as these registers are shared system
control blocks and should instead be modeled as syscon devices.
Linux has since corrected this by introducing syscon-based bindings for
the MPFS mailbox and updating the mailbox driver to access the control
and interrupt registers via syscon/regmap. U-Boot, however, continued to
expect the legacy binding, causing mailbox access to fail when using
Linux-aligned devicetrees.
Update the U-Boot MPFS mailbox driver to support the new syscon-based
bindings by resolving the control and sysreg syscon nodes and accessing
the registers through regmap. Support for the legacy mailbox binding is
retained for backwards compatibility with existing firmware-provided
devicetrees.
This brings the U-Boot mailbox driver in line with the corrected hardware
description and matches the behavior of the Linux mailbox driver.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
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Remove an unused and invalid struct mbox_chan pointer from the private
data and fix incorrect memory handling in the probe path, where the
private data structure was allocated.
This change corrects a functional bugs and cleans up the driver without
altering its behavior.
Fixes: 111e9bf6a5ac ("mailbox: add PolarFire SoC mailbox driver")
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
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The MPFS mailbox driver declares priv_auto but also allocates a second
private data structure in the legacy probe path and overwrites the
device’s private pointer using dev_set_priv().
This results in leaking the auto-allocated private data and replacing
the driver’s private state mid-probe, which is incorrect usage of the
U-Boot Driver Model and can lead to undefined behavior.
Remove the redundant allocation and dev_set_priv() call so that the
driver consistently uses the auto-allocated private data provided by
U-Boot.
Fixes: 111e9bf6a5ac ("mailbox: add PolarFire SoC mailbox driver")
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
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Correct the MMIO mapping size calculation, which
previously relied on an invalid start/end subtraction.
This change corrects a functional bug and cleans up the driver without
altering its behavior.
Fixes: 111e9bf6a5ac ("mailbox: add PolarFire SoC mailbox driver")
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
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Prepare v2026.07-rc4
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Enable the Rockchip reset controller driver in SPL to allow resetting
attached devices like UFS during early boot.
Reviewed-by: Jonas Karlman <[email protected]>
Signed-off-by: Alexey Charkov <[email protected]>
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The CLK_REF_USB3OTGx clocks are used as reference clocks for the two
DWC3 blocks.
Add simple support to get rate of CLK_REF_USB3OTGx clocks to fix
reference clock period configuration.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The CLK_REF_USB3OTG clock is used as reference clock for the DWC3 block.
Add simple support to get rate of CLK_REF_USB3OTG clock to fix reference
clock period configuration.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Implement the rst_reset operation in the ZynqMP reset driver to use
PM_RESET_ACTION_PULSE. This allows the reset controller to perform
a reset pulse in a single firmware call instead of separate assert
and deassert calls.
This matches the Linux kernel implementation of zynqmp_reset_reset().
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/be77d6f1b60f591ef626c14229d85c5cab867967.1779709539.git.michal.simek@amd.com
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Use the new reset_reset_bulk() API to properly cycle reset signals
during probe instead of just deasserting them. This ensures the
controller is properly reset before initialization.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/92e614075d2c4820d3e4485aa0bdda11efd1f7ca.1779709539.git.michal.simek@amd.com
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Add a sandbox reset controller compatible string
"sandbox,reset-ctl-fallback-only" that reuses the existing sandbox assert,
deassert, request, and free helpers but omits rst_reset. That forces
reset_reset() through the core assert / udelay / deassert fallback.
Extend the reset-ctl-test DT node with a fifth reset line named "fallback"
that points at the new provider, and add dm_test_reset_reset_fallback_path
which verifies sandbox_reset_get_count() stays zero (rst_reset is never
invoked) while the line ends deasserted after reset_reset().
This complements the existing rst_reset coverage on sandbox,reset-ctl and
matches the approach of using a separate controller to exercise the
fallback path in unit tests.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c1d40db6e2332a8b23ba842385b3f8c3d0290109.1779709539.git.michal.simek@amd.com
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Add DM test coverage for the new reset_reset() and reset_reset_bulk()
API functions.
The sandbox reset driver implements rst_reset so these tests exercise that
op (not the assert/udelay/deassert fallback in reset_reset()).
reset_reset_bulk() calls reset_reset() on each bulk entry in order, so each
line's rst_reset runs in sequence.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/be5411daf0de8eb64fbddf06e8ad82f50066e811.1779709539.git.michal.simek@amd.com
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Add reset_reset() and reset_reset_bulk() functions to the reset
controller API. These functions assert and then deassert reset signals
in a single call, providing a convenient way to pulse/toggle a reset
line.
This mimics the Linux kernel's reset_control_reset() and
reset_control_bulk_reset() APIs. The new functions are useful for
drivers that need to cycle a reset line during initialization or
error recovery but with also passing delay parameter.
If a driver implements the rst_reset op, it will be called directly
with the delay parameter. Otherwise, the reset core performs
reset_assert(), optional udelay(), and reset_deassert() as fallback.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/55ddd313c9e7b2d4dc79ab36bdd0040f871610f6.1779709539.git.michal.simek@amd.com
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Add zynqmp_pm_get_pmc_global_pggs_reg() to read PMC Global PGGS3
and PGGS4 registers via firmware IOCTL. Supports IOCTL_READ_PGGS
as the preferred path and falls back to IOCTL_READ_REG for older
PLM firmware versions that do not support IOCTL_READ_PGGS.
Signed-off-by: Padmarao Begari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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%s/requird/required/
%s/current XHCI/currently XHCI/
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Heinrich Schuchardt <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30357
- Several conversions to OF_UPSTREAM.
- Improvements for TQMa6UL boards.
- Add iMX8MP UltraLite Part CPU type.
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Signed-off-by: Alexander Feilke <[email protected]>
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Retrofit from upstream linux to try resetting the device after power loss.
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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Use previously ignored quartz-load-femtofarads property from device tree
to set load capacitance. If missing, leave the device unconfigured
as a default might have been set. force_cap is left out for now but
can be retrofitted in the future as there may be different hardware
without the 12.500pF flag.
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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Sync from upstream linux v6.19.
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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Sync definitions from upstream linux v6.19.
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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