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When enabling BLOCK_CACHE on devices with limited RAM during SPL,
some devices may not boot. This creates an option to enable
block caching in SPL by defaults off. It is dependent on SPL_BLK
Fixes: 46960ad6d09b ("block: Have BLOCK_CACHE default to y in some cases")
Signed-off-by: Adam Ford <[email protected]>
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This adds DM_GPIO support for the davinici GPIO driver with
DT support.
Signed-off-by: Adam Ford <[email protected]>
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The naming with "UART" is obviously wrong, we fix this here.
Signed-off-by: Hannes Schmelzer <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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This adds a DM video driver for U-Boot as the EFI payload. The driver
makes use of all necessary information from the passed EFI GOP info
to create a linear framebuffer device, as if it were initialized by
U-Boot itself.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Anatolij Gustschin <[email protected]>
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This function is used only inside this driver that's why should be
static.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This issue was found when OF_LIVE was enabled that there are scrambled
chars on the console like this:
Chip ID: zu3eg
Watchdog: Started��j� sdhci@ff160000: 0, sdhci@ff170000: 1
In: serial@ff010000
I found a solution for this problem exactly the same as I found later in
serial_msm fixed by:
"serial: serial_msm: initialize uart only before relocation"
(sha1: 7e5ad796bcd65772a87da236ae21cd536ae3a4d2)
What it is happening is that output TX fifo still contains chars to be
sent and _uart_zynq_serial_init() resets TX fifo even in the middle of
transfer.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Change logic and put char to fifo till there is a space in output fifo.
Origin logic was that output fifo needs to be empty. It means only one
char was in output queue.
Also remove unused ZYNQ_UART_SR_TXEMPTY macro.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Coding style is checking to use BIT macros instead of shifts.
The patch is also fixing the rest of macros which should be BITs instead
of hex numbers.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Use u32 instead of int for max_bank, bank_min and bank_max. These values
can't be negative that's why no reason to use signed type.
Signed-off-by: Michal Simek <[email protected]>
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Code around tuning_loop_counter variable expects to go below zero.
That's why this variable can't use unsigned type.
Signed-off-by: Michal Simek <[email protected]>
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There is no reason to check that unsigned type that is >= 0.
Signed-off-by: Michal Simek <[email protected]>
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This patch fixes the mmc tuning command failures
when tuning pattern data needs to read back for
comparision against the expected bit pattern.
Reported-by: Masahiro Yamada <[email protected]>
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Tested-by: Masahiro Yamada <[email protected]>
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This function is required for adding bootstage support.
Also enable it directly for ZynqMP R5 configuration.
Signed-off-by: Michal Simek <[email protected]>
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Sync the PFC tables with Linux v4.17.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Sync the PFC tables with Linux v4.17.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add missing RPC entry into the R8A77995 clock driver tables.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add missing RPC entry into the R8A77990 clock driver tables.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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struct sunxi_ccm_reg doesn't have ahb_reset0_cfg on sun4i and sun5i,
thus compilation fails with:
drivers/usb/host/ohci-sunxi.c:96:26: error: 'struct sunxi_ccm_reg' has
no member named 'ahb_reset0_cfg'
Access this reg using its offset to fix this issue.
Fixes commit 1ed9c1118 ("usb: sunxi: ehci: get rid of ifdefs")
and commit 56830cee3 ("usb: sunxi: ohci: get rid of ifdefs")
Signed-off-by: Vasily Khoruzhick <[email protected]>
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Functions can return NULL in case of error that's why checking return
value is needed.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In case of phyread()/phy_setup_op() timeout code is working with
uninitialized phyreg variable. Initialize this variable to make sure
that code it not working with random value.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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wait_for_bit_le32 returns negative value on failure. Fix phy...() to
handle these failures properly.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Combine repeated code from smi_reg_read/smi_reg_write into a common
function smi_wait_ready.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Chris Packham <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block,
the DMA reset never succeeds when a MII PHY is used (no problem with a
GMII PHY). The designware_eth_init() function sets the
DMAMAC_SRST bit in the DMA_BUS_MODE register, and then
polls until this bit clears. When a MII PHY is used, with the current
driver, this bit never clears and the driver therefore doesn't work.
The reason is that the PS bit of the GMAC_CONTROL register should be
correctly configured for the DMA reset to work. When the PS bit is 0,
it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells
the MAC we have a MII PHY.
Doing a DMA reset clears all registers, so the PS bit is cleared as
well. This makes the DMA reset work fine with a GMII PHY. However,
with MII PHY, the PS bit should be set.
We have identified this issue thanks to two SPEAr600 platform:
- One equipped with a GMII PHY, with which the existing driver was
working fine.
- One equipped with a MII PHY, where the current driver fails because
the DMA reset times out.
Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html
Signed-off-by: Quentin Schulz <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.
Signed-off-by: Chris Packham <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This makes sure the DMA buffers are properly aligned for the
hardware.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Jon Nettleton <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add driver for Socionext AVE ethernet controller that includes MAC and
MDIO bus supporting RGMII/RMII modes.
The driver behaves the ethernet driver model (DM_ETH) with devicetree.
Signed-off-by: Kunihiko Hayashi <[email protected]>
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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VCAP tables must be initialized even if no advanced classification
is used. If no initialization is performed, then ECC error will
be observed by the user when the first packet enters the l2switch.
The error is marked in MPIC_EISR0 -bit 29 which means - Internal RAM
multi-bit ECC error.
This patch fixes the aforementioned ECC error by performing the
initialization of VCAP tables.
Signed-off-by: Radu Bulie <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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If you send a final packet just before stopping the interface (e.g. a final
ACK as part of the UDP fastboot protocol), then that packet isn't reliably
delivered onto the wire.
Reap packets prior to stopping the interface to ensure any which are
in-flight make it out. Also remove buffer and len from the call to
cpdma_process() as we weren't using them on their return.
Signed-off-by: Alex Kiernan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add support for Cortina CS4223 10G PHY
- As per the CS4223 specs, an EEPROM module is
connected to the PHY. At startup the PHY reads
the firmware line and tries to load the firmware
into the internal memory.
- This driver reads the EEPROM status
and checks if firmware has been loaded
Signed-off-by: Vicentiu Galanopulo <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Put the enetaddr data in the same order as it was before the change in
commit ace1520cb5fc ("net: sunxi-emac: Write HW address via function")
Reported-by: Udo Maslo <[email protected]>
Signed-off-by: Joe Hershberger <[email protected]>
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Bus translations should be applied when reading the address of the sgmii
phy registers from the DT. Use ofnode_get_addr_index instead of the
plain ofnode_read_u32_default to fix this.
Signed-off-by: Mario Six <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Often during debugging session it's very interesting to see
what data we were dealing with. For example what we write or read
to/from memory or peripherals.
This change introduces functions that allow to dump binary
data with one simple function invocation like:
------------------->8----------------
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
------------------->8----------------
which gives us the following:
------------------->8----------------
00000000: f2 b7 c9 88 62 61 75 64 72 61 74 65 3d 31 31 35 ....baudrate=115
00000010: 32 30 30 00 62 6f 6f 74 61 72 67 73 3d 63 6f 6e 200.bootargs=con
00000020: 73 6f 6c 65 3d 74 74 79 53 33 2c 31 31 35 32 30 sole=ttyS3,11520
00000030: 30 6e 38 00 62 6f 6f 74 64 65 6c 61 79 3d 33 00 0n8.bootdelay=3.
00000040: 62 6f 6f 74 66 69 6c 65 3d 75 49 6d 61 67 65 00 bootfile=uImage.
00000050: 66 64 74 63 6f 6e 74 72 6f 6c 61 64 64 72 3d 39 fdtcontroladdr=9
00000060: 66 66 62 31 62 61 30 00 6c 6f 61 64 61 64 64 72 ffb1ba0.loadaddr
00000070: 3d 30 78 38 32 30 30 30 30 30 30 00 73 74 64 65 =0x82000000.stde
00000080: 72 72 3d 73 65 72 69 61 6c 30 40 65 30 30 32 32 rr=serial0@e0022
00000090: 30 30 30 00 73 74 64 69 6e 3d 73 65 72 69 61 6c 000.stdin=serial
000000a0: 30 40 65 30 30 32 32 30 30 30 00 73 74 64 6f 75 [email protected]
000000b0: 74 3d 73 65 72 69 61 6c 30 40 65 30 30 32 32 30 t=serial0@e00220
000000c0: 30 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00..............
...
------------------->8----------------
Source of hexdump.c was copied from Linux kernel v4.7-rc2.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Stefan Roese <[email protected]>
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On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
clock when OHCI1 is in use.
Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
Signed-off-by: Vasily Khoruzhick <[email protected]>
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We can use compatibles instead.
Signed-off-by: Vasily Khoruzhick <[email protected]>
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We can use compatibles instead.
Signed-off-by: Vasily Khoruzhick <[email protected]>
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If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.
This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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If we use U-Boot as coreboot payload with a generic dts without
any ranges specified we fail in pci pre_probe and our pci bus
is not usable.
So convert decode_regions(..) into a void function and do the simple
error handling there.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: fixed 'u-boot' in the commit message and checkpatch warning]
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This fixes the following compiler warning:
"warning: cast from pointer to integer of different size
[-Wpointer-to-int-cast]"
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.
This fixes booting on a skylake based system.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng <[email protected]>
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Added the following:
1. defconfig for LS1012AFRWY Secure boot
2. PfE Validation support
Signed-off-by: Vinitha V Pillai <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add WARN_ONCE definition to allow single time notification
of warnings to the user.
Taken from Linux kernel (4.17) with slight changes
(Removed __section(.data.once))
Signed-off-by: Ramon Fried <[email protected]>
[trini: Drop the musb and dwc3 compat versions]
Signed-off-by: Tom Rini <[email protected]>
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When dealing with filesystems that come from block devices we can get a
noticeable performance gain in some use cases from having the block
cache enabled. The code paths are valid in other cases when we have BLK
set and may provide wins in raw reads in some use cases, so have this be
default when BLK is enabled.
Signed-off-by: Tom Rini <[email protected]>
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