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The thor sender can send filename without null character and it is
used without consideration of overflow. Actually, character array
for filename is assigned with DEFINE_CACHE_ALIGN_BUFFER() and it
is bigger than size of memcpy, so there was no real overflow.
Fix filename overflow for code level integrity.
Signed-off-by: Seung-Woo Kim <[email protected]>
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This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
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Add DDR driver support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
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Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.
Signed-off-by: Tien Fong Chee <[email protected]>
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This change enables support for MC34708 PMIC in sandbox. Now we can
emulate the I2C transfers larger than 1 byte.
Notable changes for this driver:
- From now on the register number is not equal to index in the buffer,
which emulates the PMIC registers
- The PMIC register's pool is now dynamically allocated up till
64 regs * 3 bytes each = 192 B
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch adds support for MC34708 PMIC, to be used with driver model
(DM).
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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transmissions
This commit provides support for transmissions larger than 1 byte for
PMIC devices used with DM (e.g. MC34708 from NXP).
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The struct uc_pmic_priv's trans_len field stores the number of types to
be transmitted per PMIC transfer.
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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When Kconfig support was added for MVGBE it included automatically
selected PHYLIB support. But MVGBE does not need PHYLIB it will build
fine without it. Commit ed52ea507f12 ("net: add Kconfig for MVGBE")
should have been a no-op in terms of build size but because of the
selecting PHYLIB the openrd configs increased in size.
Remove the automatic selection of PHYLIB, boards that need it will have
already enabled it in their config header file.
Fixes: commit ed52ea507f12 ("net: add Kconfig for MVGBE")
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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In
void *rx_addr = NULL;
rx_add = A;
the first assignment has no effect. Remove it.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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A & A & B == A & B
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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For SPI_XFER_BEGIN | SPI_XFER_END the code sets data_out = NULL.
In the debug statement we should not dereference this value.
As we do not transfer any data the debug statement is not needed in this
case anyway.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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page size for JEDEC EXT starting 0x4d00 is 512b,
except JEDEC ID 0x215, 0x216 and 0x220
Signed-off-by: Ashish Kumar <[email protected]>
[jagan: added proper commit message]
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Added support for is25wp032, is25wp064 and is25wp128.
Signed-off-by: Kimmo Rautkoski <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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In some situation, QSPI controller is already configured by an early
boot stage, adding reset support will insure that QSPI controller is
started from a pristine state.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Use dev_read_xxx() instead of old manner fdt_xxx() API
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Quad-SPI interface is able to manage 2 spi nor devices.
FSEL bit selects the flash memory to be addressed in single flash mode.
Signed-off-by: Christophe Kerello <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add "st,stm32f469-qspi" compatible which is used on kernel side.
This will be necessary when DT will be synchronised from kernel.
Signed-off-by: Christophe Kerello <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.12-rc1.
Signed-off-by: Christophe Kerello <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Sort include files by alphabetical order
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Fix parameters function alingemnt
Fix variable declaration
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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As all platforms which uses this driver have CONFIG_CLK flag
enable in their defconfig, we can remove it from driver code.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Not all the udevice have a available DT node, eg. [email protected]
which add by mmc_bind(), these device do not have/need set pinctrl
state.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h
To address that situation we discussed on the list moving to
genetic_set_bit() instead.
Doing a quick grep for similar situations in drivers/usb shows that the
composite device is using __set_bit().
This patch switches over to generic_set_bit to maintain consistency between
the two gadget drivers.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Marek Vasut <[email protected]>
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Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h
Looking at the provenance of the current u-boot code and the git change
history in the kernel, it looks like we have a local copy of set_bit and
clear_bit as a hold-over from porting the Linux driver into u-boot.
These days __set_bit and __clear_bit are optionally provided by an arch and
can be used as inputs to generic_bit_set and generic_bit_clear.
This patch switches over to generic_set_bit and generic_clear_bit to
accommodate.
Tested on i.MX WaRP7 and Intel Edison
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Marek Vasut <[email protected]>
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mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code.
When imported into u-boot we need to add the appropriate SPDX tag and
re-format it slightly.
Signed-off-by: Chris Packham <[email protected]>
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This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)
Signed-off-by: Vasily Khoruzhick <[email protected]>
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Currently dw_hdmi configures HSYNC polarity using VSYNC setting from
EDID and vice versa. Fix it, since it breaks displays where HSYNC
and VSYNC polarity differs
Signed-off-by: Vasily Khoruzhick <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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HSYNC is bit 8, and VSYNC is bit 9.
Signed-off-by: Vasily Khoruzhick <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The check is necessary to avoid NULL pointer dereference.
Signed-off-by: Ramon Fried <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
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Add Kconfig for MVGBE and update boards to select this.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Nothing defines CONFIG_DOVE so remove the code that uses it.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975
(rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC)
Ethernet no longer probes on RK3288.
Add no-ops for GMAC clocks observed to be requested which match the
clk_enable cases in RK3368 and RK3399.
Signed-off-by: Jonathan Gray <[email protected]>
Cc: Wadim Egorov <[email protected]>
Cc: Philipp Tomsich <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".
Signed-off-by: Marek Behun <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT
INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.
Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or
STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to
remove unused sections in the rest of the ddr/marvell/a38x code.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This adds support for the CPU watchdog found on Marvell Armada 37xx
SoCs.
There are 4 counters which can be set as CPU watchdog counters.
This driver uses the second counter (ID 1, counting from 0)
(Marvell's Linux also uses second counter by default).
In the future it could be adapted to use other counters, with
definition in the device tree.
Signed-off-by: Marek Behun <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The driver does not check id phy_connect failed (for example on wrong
property name in device tree). In such a case a fault occurs and the
CPU is restarted.
Signed-off-by: Marek Behun <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Move the reg_set* functions into comphy.h as static inline functions.
Change return type of get_*_string to const char *.
Signed-off-by: Marek Behun <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Add support for the clk dump command on Armada 37xx.
Signed-off-by: Marek Behun <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Since now we have driver for clocks on Armada 37xx, use it to determine
SQF clock frequency for the SPI driver.
Also change the default config files for Armada 37xx devices so that
the clock driver is enabled by default, otherwise the SPI driver cannot
be enabled.
Signed-off-by: Marek Behun <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The drivers are based on Linux driver by Gregory Clement.
The TBG clocks support only the .get_rate method.
- since setting rate is not supported, the driver computes the rates
when probing and so subsequent calls to the .get_rate method do not
read the corresponding registers again
The peripheral clocks support methods .get_rate, .enable and .disable.
- the .set_parent method theoretically could be supported on some clocks
(the parent would have to be one of the TBG clocks)
- the .set_rate method would have to try all the divider values to find
the best approximation of a given rate, and it doesn't seem like
this should be needed in U-Boot, therefore not implemented
Signed-off-by: Marek Behun <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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