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Add the SCIFA0 address entry so it can be used in TPL if needed
due to size restrictions.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add compatible strings for R8A7790, R8A7793 and R8A7794, since the
contemporary DTs use those don't have a generic match value.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Joe Hershberger <[email protected]>
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The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks
is also not used in U-Boot, so drop it too.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Some boards expect to find more than one phy while other boards are old
and need to be limited to a specific phy address. Only limit the phy
address for boards that opt in.
Signed-off-by: Joe Hershberger <[email protected]>
Tested-by: Bin Meng <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add compatible strings for R8A7790, R8A7793 and R8A7794, since the
contemporary DTs use those don't have a generic match value.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add support to use max-speed property from dt for
determining the supported speed. Use 1000Mbps as
default.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Since the probe function has changed to reset FEC controller prior than
setup PHY. If reset FEC controller timeout, the priv->phydev is not
initialized, so can't free it.
Signed-off-by: Ye Li <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add i.MX6UL/SX/SL compatible.
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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On i.MX6SX, 6UL and 7D, there are two enet controllers each has a
MDIO port. But Some boards share one MDIO port for the two enets. So
introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate
the MDIO port for sharing.
In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter
the CONFIG_FEC_MXC_MDIO_BASE.
To i.MX28, adapt to use the new config
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Cc: Fabio Estevam <[email protected]>
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To platforms has two enet interface, using dev->seq could
avoid conflict.
i.MX6UL/ULL evk board net get the wrong MAC address from fuse,
eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the
priv->dev_id to device->seq as the real net interface alias id then
.fec_get_hwaddr() read the related MAC address from fuse.
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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No need to provide two prototype for this function.
Use ulong for the first parameter, then this function
could be shared for DM/non DM case.
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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When using ethernet DM driver, the recv interface has a
change with non-DM interface, that driver needs to set
the packet pointer and provide it to upper layer to process.
In fec driver, the fecmxc_recv functions does not handle the
packet pointer parameter. This may cause crash in upper layer
processing because the packet pointer is not set.
This patch allocates a buffer for the packet pointer and free it
through free_pkt interface.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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mvneta already supports setting the MAC address but this was only done
internally when some other part of U-Boot tries to actually use the
interface. This commit exposes this functionality to the ethernet core
code so that the MAC addresses of all interfaces are configured
correctly even if they are not used before loading Linux.
Signed-off-by: Matt Pelland <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The dwc_ahci has been broken for quite some time now. The breakage has been
introduced by the series "dm: scsi: Enhance SCSI support for driver model"
Use ahci_bind_scsi() and ahci_probe_scsi() to properly bind and probe the
driver.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
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The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing
the SPI transmission 1 byte at time, if there is a 32byte chunk of
data to be transferred, fill the FIFO completely and then transfer
the data to/from the FIFO. This increases the SPI NOR access speed
significantly.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Replace the ad-hoc endless loops with wait_for_bit() with
reasonable timeout. Note that the loops had internal 10uS
delays, although there is no reason for those on this HW,
so they are dropped.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Waiting for SPBDCR == 1 is not required and is covered by the
subsequent wait for SPSR_SPRFF, so drop this.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Just replace unsigned {char,short,long} with u{8,16,32},
no functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add driver for the RPC block in Hyperflash mode. This driver allows
access to a CFI Hyperflash attached to the RPC block and does not
support RPC in SPI mode.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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The IP requires some time to recuperate after the IO pin
properties were changed. Add a delay to assure this.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Fix minor rebase omission, the else was missing which triggered
two accesses to the register on 64bit variant of the IP.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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The HOST_MODE register must be set to 0 when the IP is operated in 16bit
mode, otherwise 16bit access to the data FIFO may fail.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Export the matsu_sd_{read,write}l() common register access
functions, so that they can be used by other drivers sharing
the common code.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Factor out the regulator handling into set_ios and add support for
selecting pin configuration based on the voltage to support UHS modes.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Handle bus width 0 as 1-bit bus to assure valid content of
MATSU_SD_OPTION register WIDTH field.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Drop the ad-hoc DT caps parsing in favor of common framework function.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Drop useless check in matsu_sd_{read,write}q(), this is only ever
called to read the data from FIFO and only when 64bit variant of
the block is used anyway.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Add macros to generate the FIFO accessors, since the code is almost
the same with only minor differences. This is done in preparation
for adding 16bit variant of the IP.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Add Kconfig entry for the Renesas SDHI variant of the controller
and split the Makefile entries accordingly.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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Factor out common code from the uniphier SD driver, change the prefix
of the functions from uniphier_sd_ to matsu_sd_ and create separate
renesas-sdhi.c driver. Thus far, all the code is still compiled when
CONFIG_UNIPHIER_MMC is selected and there is no functional change.
This patch is a preparation for further split of the SoC specific
parts of the Matsushita SD driver, used both on Uniphier and R-Car.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Masahiro Yamada <[email protected]>
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This patch fixes a situation where CONFIG_DM_SERIAL is enabled for
regular U-Boot and SPL, but not for TPL. In that case, the build
will try to include serial-uclass into the TPL nonetheless, because
CONFIG_DM_SERIAL is set.
The solution is to check if the build is for SPL or TPL and in that
case, check if CONFIG_$(SPL_TPL_)DM_SERIAL is also set. Only in that
case, include serial-uclass.c . If the build is for regular U-Boot,
CONFIG_BUILD is not set, so only check if CONFIG_DM_SERIAL is set
and if so, include serial-uclass.c
Signed-off-by: Marek Vasut <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
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The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs
and an USB3 PHY. This patch adds drivers for these for the standard generic
PHY interface and supports the power-on/off calls and set the Host mode by
default.
They are based on the excellent work from Martin Blumenstingl merged in linux.
Signed-off-by: Neil Armstrong <[email protected]>
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DWC3 Ips can have more than 1 PHY for USB2 and 1 PHY for USB3, add support
for a generic number of PHYs and adapt the code to handle a generic
number of PHYs.
Signed-off-by: Neil Armstrong <[email protected]>
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This is a port of the dwc3-of-simple driver from Linux to enable/deassert
clock and resets of a simple DWC3 Controller HW glue.
Signed-off-by: Neil Armstrong <[email protected]>
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Add an option to get the clock speed from the device tree, hence adding
compatibility with DM clock drivers.
Signed-off-by: Mario Six <[email protected]>
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Since bus translations are now fully supported, use a plain
"dev_read_addr" to get the device address from the device tree.
Signed-off-by: Mario Six <[email protected]>
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