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In January some commits were introduced to mitigate the U-Boot image
size issues we encountered on sunxi builds.
Now with the MMC environment removed we can bring them back, as we
practically don't have a size limit anymore.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The original DT binding used by U-Boot's sun8i-emac driver was not really
agreed upon, and deviated from the "official" binding now used by the
kernel. Since now all U-Boot users have been converted to the new
binding, we can remove support for the old DT nodes from the driver.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an
upstream Linux driver in v4.15.
This one uses a slightly different binding from the original one used
by the U-Boot driver.
The differences to the old binding are:
- The "syscon" address is held in a separate node, referenced via a
phandle in the "syscon" property.
- The reference to the PHY is held in a property called "phy-handle",
not "phy".
- The PHY register is at offset 0x30 in the syscon device, not at 0.
- The internal PHY is activated when the node, which phy-handle points
to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node.
Teach the U-Boot driver how to find its resources in a "new-style" DT,
so that we can use a Linux kernel compatible DT for U-Boot as well.
This keeps support for the old binding for now, to allow a smooth
transition.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The Linux kernel driver for the Allwinner pin controller gained support
for generic properties, which are now also used in the DTs.
The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from
the DT, but so far only supported the old binding.
Update the parsing routine to cope with both the old and new bindings,
so that the newer DTs can be used with U-Boot and its Ethernet driver.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The sunxi GPIO driver is missing some compatible strings for recent
SoCs. While most of the sunxi GPIO code seems to not rely on this (and
so works anyway), the sunxi_name_to_gpio() function does and fails at
the moment (for instance when resolving the MMC CD pin name).
Add the compatible strings for the A64 and V3s, which were missing
from the list. This now covers all pinctrl nodes in our own DTs.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.
It would have been better to convert this defconfig entry to Kconfig for
all supported machines/architectures but it has been abandoned due to a
fairly high amount of errors reported by the moveconfig.py tool. This is
due to defines quite often being multiplications of values/other defines
not correctly handled.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND support.
For now, the only board using it is the CHIP pro.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.
Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.
There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.
The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Executing a command is matter of always doing the following sequence:
* Waiting for the FIFO to be empty so we can fill it with the new
command.
* Clearing the status register.
* Writing the command in the FIFO.
* Waiting for the command to finish.
Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.
Add this sanity check before starting any new command.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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The pattern of polling on a status register until a bit is set or a
timeout occurs is repeated multiple times in the driver. Mutualize the
code by introducing the nand_wait_int() helper that does wait for the
bit to flip or returns an error in case of timeout.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Change NFC_SEND_ADR to NFC_SEND_ADDR.
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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In the nand_read_buffer() step, the seed is calculated by doing a modulo
by conf->nseeds which is always zero when not using the randomizer (most
of SLC NANDs).
This situation turns out to lead to a run time freeze with certain
toolchains.
Derive this seed only when the randomizer is enabled (and conf->nseeds
logically not zero), exactly like what has been done before with an
identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo
by zero error").
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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When the requested ECC strength does not exactly match the strengths
supported by the ECC engine, the driver is selecting the closest
strength meeting the 'selected_strength > requested_strength'
constraint. Fix the fact that, in this particular case, ecc->strength
value was not updated to match the 'selected_strength'.
For instance, one can encounter this issue when no ECC requirement is
filled in the device tree while the NAND chip minimum requirement is not
a strength/step_size combo natively supported by the ECC engine.
Suggested-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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Commit 286ede6 ("drivers: core: Add translation in live tree case") made
dev_get_addr always use proper bus translations for addresses read from
the device tree. But this leads to problems with certain busses, e.g.
I2C busses, which run into an error during translation, and hence stop
working.
It turns out that of_translate_address() and fdt_translate_address()
stop the address translation with an error when they're asked to
translate addresses for busses where #size-cells == 0 (comment from
drivers/core/of_addr.c):
* Note: We consider that crossing any level with #size-cells == 0 to mean
* that translation is impossible (that is we are not dealing with a value
* that can be mapped to a cpu physical address). This is not really specified
* that way, but this is traditionally the way IBM at least do things
To fix this case, we check in both the live-tree and non-live tree-case,
whether the bus of the device whose address is about to be translated
has size-cell size zero. If this is the case, we just read the address
as a plain integer and return it, and only apply bus translations if the
size-cell size if greater than zero.
Signed-off-by: Mario Six <[email protected]>
Signed-off-by: Martin Fuzzey <[email protected]>
Reported-by: Martin Fuzzey <[email protected]>
Fixes: 286ede6 ("drivers: core: Add translation in live tree case")
Reviewed-by: Simon Glass <[email protected]>
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dm_scan_fdt_node can't work when live dt is active,
we should use dm_scan_fdt_live instead.
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Use live dt interface for pinctrl_select_state_full()
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add api for who can not get phandle from a device property.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.
Signed-off-by: Wilson Ding <[email protected]>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu <[email protected]>
Reviewed-by: Hua Jing <[email protected]>
Tested-by: Hua Jing <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Ken Ma <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch corrects below mpp definitions:
- The sdio_sb group is composed of 6 pins and not 5;
- The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
- Pin of group "pmic0" is mpp1[6] but not mpp1[16];
- Pin of group "pmic1" is mpp1[7] but not mpp1[17];
- A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
bitmask is bit4;
- Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
bit5 | bit9 | bit10 but not bit4;
- Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
bit11 | bit12 | bit13.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Hua Jing <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Ken Ma <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Ken Ma <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Pin 23 on South bridge does not belong to the rgmii group. It belongs to
a separate group which can have 3 functions.
Due to this the fix also have to update the way the functions are
managed. Until now each groups used NB_FUNCS(which was 2) functions. For
the mpp23, 3 functions are available but it is the only group which needs
it, so on the loop involving NB_FUNCS an extra test was added to handle
only the functions added.
The bug was visible when the gpio regulator used the gpio 23, the whole
rgmii group was setup to gpio which broke the Ethernet support on the
Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need
the vqmmc) _and_ the Ethernet work again.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43284
Reviewed-by: Hua Jing <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Ken Ma <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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On the south bridge we have pin from 0 to 29, so it gives 30 pins (and
not 29).
Reviewed-on: http://vgitil04.il.marvell.com:8080/43285
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Hua Jing <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Ken Ma <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Currently, ATU (address translation unit) implementation doesn't
support translate addresses > 32 bits.
This patch allows to configure ATU correctly for different
memory accesses (memory, configuration and IO).
The same approach is used in Linux Kernel.
Signed-off-by: Igal Liberman <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Use dm_pci_map_bar function for BAR mapping. This has the advantage
of clearing BAR flags and and only accepting mapped memory.
Signed-off-by: Bernhard Messerklinger <[email protected]>
Reviewed-by: Hannes Schmelzer <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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It makes no sense to set a PCI region that has 0 size.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.
With this commit, Intel Galileo board boots again.
Fixes: 664758c ("pci: Fix decode regions for memory banks")
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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nsd32_mmc was created to support ftsdc010 dm.
It is not necessary to separate both, so merge it
to ftsdc010.
Signed-off-by: Rick Chen <[email protected]>
Signed-off-by: Rick Chen <[email protected]>
Cc: Greentime Hu <[email protected]>
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Convert CONFIG_FTSDC010_SDIO to Kconfig.
So CONFIG_FTSDC010_SDIO can also be
removed from config_whitelist.txt.
Signed-off-by: Rick Chen <[email protected]>
Signed-off-by: Rick Chen <[email protected]>
Cc: Greentime Hu <[email protected]>
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Only three defconfig(adp-ag101p_defconfig,
adp-ae3xx_defconfig, nx25-ae250_defconfig)
set CONFIG_FTSDC010=y. And they all also
enable CONFIG_DM_MMC. So the non-dm code
of ftsdc010 can be dropped now.
Signed-off-by: Rick Chen <[email protected]>
Signed-off-by: Rick Chen <[email protected]>
Cc: Greentime Hu <[email protected]>
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ftsdc010 dm driver has been disable High-Speed mode
as default to work around Andes AE3XX platform's problem,
because of it does not support High-Speed mode in
commit id 73cd56b2df213c629191139e5c6705e069b6214f.
But other platforms or SoCs maybe support this function.
So High-Speed mode can be enabled from dts with
cap-mmc-highspeed or cap-sd-highspeed property.
Signed-off-by: Rick Chen <[email protected]>
Signed-off-by: Rick Chen <[email protected]>
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Existing driver supports upto 4 I2C controllers.
But some of future NXPs SoCs like lx2160a has
eight I2C controllers.
Update MXC driver to support upto 8 I2C controllers
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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NXP layerscape platforms like ls1088a, ls2088a
uses MXC I2C Controller.
-Remove dependency of MX6 for the same.
Update related configs to use Kconfig file.
-Add SYS_I2C_MXC_I2C1,_I2C2,_I2C3,_I2C4 in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SPEED,_I2C2_,_I2C3_,_I2C4_ in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SLAVE,_I2C2_,_I2C3_,_I2C4_ in Kconfig
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
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The Rockchip-specific SDHCI wrapper does not process the 'bus-width'
property in the SDHCI node. Consequently, the bus is always kept in
4bit mode, even if 8bit wide operation is available, supported and
requested in the DTS.
This change adds processing of the 'bus-width' property and sets the
host capability flag for an 8bit wide bus, if set to 8. As the logic
in sdhci.c does not support clearing the 4bit capability, we assume
that 4bit operation is always supported.
Signed-off-by: Philipp Tomsich <[email protected]>
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The patch set dpll settings for 300MHz to values used by binary
blob[1]. With new values dpll still generate 300MHz clock, but
EMAC work. Probably with new values dpll generate more stable clock.
dpll on rk3188 provide clocks to DDR and EMAC. With current
dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
to network, but it doesn't receive anything. ifconfig shows a lot
of framing errors.
[1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin
Signed-off-by: Alexander Kochetkov <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Signed-off-by: Punit Agrawal <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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The error checking should also catch the case that no range has beeen
defined.
syscon_get_first_range() returns NULL if no range is defined.
cf. rk3399_mipi.c
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Signed-off-by: Punit Agrawal <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Pointers are never negative. Use macro IS_ERR() for checking.
cf. rk3288_mipi.c
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Assigning f_rkusb->reboot_flag twice doesn't make sense.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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