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If we want to check the duration we need to increment the counter.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Clean the iomux definitions at grf_rk3188.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: Alexander Kochetkov <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Clean the iomux definitions at grf_rk3036.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: Alexander Kochetkov <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This adds support for the (to date unsupported) I2C controllers 1~4
and 6~7 (i.e. now all controllers except I2C5, which is not accessible
on the RK3399-Q7, are supported by pinctrl).
Signed-off-by: Philipp Tomsich <[email protected]>
Tested-by: Klaus Goger <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
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Signed-off-by: Petr Vorel <[email protected]>
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The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.
Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This patch print pl clocks (pl0...pl3) and watchdog
clock using clk dump.
Signed-off-by: Vipul Kumar <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.
Signed-off-by: Vipul Kumar <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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This IP can be found on Zynq and ZynqMP devices.
The driver was tested with reset-on-timeout; feature.
Also adding WATCHDOG symbol to Kconfig because it is required.
Signed-off-by: Shreenidhi Shedi <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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watchdog clock is also connected to cpu 1X clocksource.
Zynq> clk dump
...
Before:
swdt 4294967290
After:
swdt 111111110
Signed-off-by: Michal Simek <[email protected]>
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This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Check !desc earlier to simplify code.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Simon Goldschmidt <[email protected]>
Reviewed-by: Simon Goldschmidt <[email protected]>
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In
lpi2c_status_t result = A;
result = B;
the first assignment has no effect. Let's remove it.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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With DM enabled in SPL, DM_FLAG_PRE_RELOC is required for
the omap_gpio driver to be bound to the gpio devices.
Therefore, add DM_FLAG_PRE_RELOC flag to the omap_gpio driver.
Signed-off-by: Faiz Abbas <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Last user of this driver went away in October 2014 in
commit d58a9451e7339ed4 ("ppc/arm: zap EMK boards").
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In
if (a > =0) {...}
else (a < 0) {...}
the second logical constraint is superfluous.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In
int ret = A;
ret = B;
the first assignment has not effect.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The lan75xx and lan78xx drivers need to drive their phy via the generic
phylib framework. Let's reflect that dependency in Kconfig, so that we
don't get build errors when phylib does not get selected.
Signed-off-by: Alexander Graf <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.
But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.
Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.
Signed-off-by: Priyanka Jain <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Update get_phy_id() implementation in cortina.c to check
for Cortina_phy by comparing device phy_id with cortina phy_id
instead of relying on presence of CORTINA macros.
This will allow get_phy_id to work with non-cortina phy devices
which might have same phy address as Cortina device but on
different bus.
Signed-off-by: Priyanka Jain <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add configurations for PFE.
Signed-off-by: Calvin Johnson <[email protected]>
Signed-off-by: Anjaneyulu Jagarlmudi <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.
Signed-off-by: Calvin Johnson <[email protected]>
Signed-off-by: Anjaneyulu Jagarlmudi <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch adds PFE driver to U-Boot
Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.
Signed-off-by: Calvin Johnson <[email protected]>
Signed-off-by: Anjaneyulu Jagarlmudi <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.
drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
phydev->dev->name);
^~
Signed-off-by: Calvin Johnson <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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After allocating plat the pointer is checked.
Afterwards name is allocated and not checked.
Add the missing check to avoid a possible NULL dereference.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off
on the PHY, as well as flipping some magical undocumented bits. The
magic number comes from the Pine64 engineering team, presumably as a
proxy from Realtek. This configuration fixes the throughput on some
Pine64 models. Packet loss of up to 60-70% has been observed without
this.
Signed-off-by: Kyle Evans <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16 and 32 bit mix
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Signed-off-by: Eugeniy Paltsev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.
So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.
With these changes we're getting closer to Linux DW SPI driver.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.
Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)
So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Make sure the user is notified instead of silently returning an error.
Signed-off-by: Liam Beguin <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
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Signed-off-by: Ãlvaro Fernández Rojas <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Signed-off-by: Ãlvaro Fernández Rojas <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Signed-off-by: Ãlvaro Fernández Rojas <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Signed-off-by: Ãlvaro Fernández Rojas <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
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Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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ppc4xx support was removed some time ago. Lets remove the now unused
NAND driver and all its references for this platform as well.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>
Cc: Scott Wood <[email protected]>
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add binding and code for clock tree initialization from device tree
Signed-off-by: Patrick Delaunay <[email protected]>
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add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
of all SOC clock needed by U-Boot
Signed-off-by: Patrick Delaunay <[email protected]>
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- move to livetree and allow to get address to parent
- add stm32mp1 compatible for probe
Signed-off-by: Patrick Delaunay <[email protected]>
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- add the 2 new compatible used by STM32MP157
"st,stm32mp157-pinctrl"
"st,stm32mp157-z-pinctrl"
- update the mask for the port
Signed-off-by: Patrick Delaunay <[email protected]>
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This driver implements register read/write operations for STPMU1.
The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF
and 2 power switches. It is accessed via an I2C interface.
This device is used with STM32MP1 SoCs.
Signed-off-by: Patrick Delaunay <[email protected]>
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Add driver and binding for stm32mp1 ddr controller and phy
Signed-off-by: Patrick Delaunay <[email protected]>
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