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Command bytes are part of the written bytes and they should be taken into
account when sending a spi transfer.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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For some SPI controllers it's not possible to keep the CS active between
transfers and they are limited to a known number of bytes.
This splits spi_flash reads into different iterations in order to respect
the SPI controller limits.
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The hash command function were not flushing the dcache before passing data
to CAAM/DMA and not invalidating the dcache when getting data back.
Due the data cache incoherency, HW accelerated hash commands used to fail
with CAAM errors like "Invalid KEY Command".
Check if pbuf and pout buffers are properly aligned to the cache line size
and flush/invalidate the memory regions to address this issue.
This solution is based in a previous work from Clemens Gruber in
commit 598e9dccc75d ("crypto/fsl: fix BLOB encapsulation and
decapsulation")
Reported-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Breno Lima <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Patch queue for efi - 2018-01-23
This time around we have a lot of EFI patches from Heinrich.
Highlights are:
- Allow EFI applications to register as drivers
- Allow exposure of U-Boot block devices from an EFI payload
- Compatibility improvements
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This patch provides
* a uclass for EFI drivers
* a EFI driver for block devices
For each EFI driver the uclass
* creates a handle
* adds the driver binding protocol
The uclass provides the bind, start, and stop entry points for the driver
binding protocol.
In bind() and stop() it checks if the controller implements the protocol
supported by the EFI driver. In the start() function it calls the bind()
function of the EFI driver. In the stop() function it destroys the child
controllers.
The EFI block driver binds to controllers implementing the block io
protocol.
When the bind function of the EFI block driver is called it creates a
new U-Boot block device. It installs child handles for all partitions and
installs the simple file protocol on these.
The read and write functions of the EFI block driver delegate calls to the
controller that it is bound to.
A usage example is as following:
U-Boot loads the iPXE snp.efi executable. iPXE connects an iSCSI drive and
exposes a handle with the block IO protocol. It calls ConnectController.
Now the EFI block driver installs the partitions with the simple file
protocol.
iPXE uses the simple file protocol to load Grub or the Linux Kernel.
Signed-off-by: Heinrich Schuchardt <[email protected]>
[agraf: add comment on calloc len]
Signed-off-by: Alexander Graf <[email protected]>
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This converts the following to Kconfig:
CONFIG_ROCKCHIP_USB2_PHY
Signed-off-by: Adam Ford <[email protected]>
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This converts the following to Kconfig:
CONFIG_OMAP_USB_PHY
Signed-off-by: Adam Ford <[email protected]>
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This converts the following to Kconfig:
CONFIG_TWL4030_USB
Signed-off-by: Adam Ford <[email protected]>
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This converts the following to Kconfig:
CONFIG_DAVINCI_SPI
Signed-off-by: Adam Ford <[email protected]>
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This converts the following to Kconfig:
CONFIG_USB_MUSB_HCD
CONFIG_USB_MUSB_UDC
CONFIG_USB_DAVINCI
CONFIG_USB_OMAP3
CONFIG_USB_DA8XX
CONFIG_USB_AM35X
Signed-off-by: Adam Ford <[email protected]>
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This converts the following to Kconfig:
CONFIG_USB_MUSB_OMAP2PLUS
CONFIG_USB_MUSB_AM35X
CONFIG_USB_MUSB_DSPS
CONFIG_USB_MUSB_PIO_ONLY
Signed-off-by: Adam Ford <[email protected]>
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flags member of struct timing was not initialized,
this took to unpredictable behaviour of display flags,
such DISPLAY_FLAGS_HSYNC_HIGH instead of _LOW etc.
Init timing->flags = 0
Signed-off-by: Giulio Benetti <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Commit 4f425280fa71 ("mmc: fsl_esdhc: Allow all supported prescaler
values") made it possible to set SYSCTL.SDCLKFS to 0 in SDR mode on
i.MX, thus bypassing the SD clock frequency prescaler, in order to be
able to get higher SD clock frequencies in some contexts. However, that
commit missed the fact that this value is illegal on the eSDHCv3
instance of the i.MX53. This seems to be the only exception on i.MX,
this value being legal even for the eSDHCv2 instances of the i.MX53.
Fix this issue by changing the minimum prescaler value for the single
instance of the i.MX53 eSDHCv3 controller.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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When power is off, clock is not disabling.
Because it's passed to 1, mmc->clock should be set to f_min value.
Some drivers can't initialize the eMMC/SD card with current status.
This patch is to fix the disabling clock value to 0.
Fixes: 2e7410d76ad1 ("mmc: disable the mmc clock during power off")
Signed-off-by: Jaehoon Chung <[email protected]>
Reviewed-by: Jean-Jacques Hiblot <[email protected]>
Tested-by: Guillaume GARDET <[email protected]>
Tested-by: Anand Moon <[email protected]>
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During the tuning, drivers repeat data transfer, changing timing
parameters in the controller hardware. So, the tuning commands
(CMD19 for SD, CMD21 for eMMC) fail, and this is not a problem
at all.
Showing "Error detected..." in normal operation just make users
upset. This should not be shown.
Signed-off-by: Masahiro Yamada <[email protected]>
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Add HS200 timing setting and the MMC tuning callback.
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
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This is needed to parse more capabilities such as mmc-hs200-1_8v.
Signed-off-by: Masahiro Yamada <[email protected]>
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This driver is a counterpart from the one in Linux. Follow the
clean-up I did in Linux.
Signed-off-by: Masahiro Yamada <[email protected]>
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This line overwrites host_cap that has been set by drivers and/or
helpers like mmc_of_parse(). Accumulate capabilities flags.
Signed-off-by: Masahiro Yamada <[email protected]>
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You must fix your DT if it specifies insane bus-width, for example,
bus-width = <3>;
debug() is not displayed in usual configuration, so people will not
even notice weirdness. Use dev_err() instead, then let it fail.
Signed-off-by: Masahiro Yamada <[email protected]>
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mmc_of_parse() in U-Boot is a pussy helper; it sets cfg->f_max to
52MHz even if DT does not provide "max-frequency" at all. This can
overwrite cfg->f_max that may have been set to a reasonable default.
As the DT binding says, "max-frequency" is an optional property.
Do nothing if DT does not specify it. This is the behavior of
mmc_of_parse() in Linux.
Signed-off-by: Masahiro Yamada <[email protected]>
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dev_read_u32_default() always returns something even when the property
is missing. So, it is impossible to do nothing in the case. One
solution is to use ofnode_read_u32() instead, but adding dev_read_u32()
will be helpful.
BTW, Linux has an equvalent function, device_property_read_u32();
it is clearer that it reads a property. I cannot understand the
behavior of dev_read_u32() from its name.
Signed-off-by: Masahiro Yamada <[email protected]>
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Judging from its name and parameters, device_is_compatible looks like it
is compatible with a live device tree, but it actually isn't.
Make it compatible with a live device tree.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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There are some whitespace-related style violations in read.c; fix those.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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There are some style violations in ofnode.c; fix those.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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The Makefile entries in the clk driver directory were not alphabetically
sorted. Correct this.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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The clk uclass was converted to support a live device tree recently,
hence the global data pointer declarations are no longer needed.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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Fix a mis-indented function call in clk_fixed_rate.c
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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checkpatch.pl complains that the clk_ops structures used in clk-uclass.c
ought to be const, so we mark them as const.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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The function dev_read_addr calls ofnode_get_addr_index in the live tree
case, which does not apply bus translations to the address read from the
device tree. This results in illegal addresses on boards that rely on
bus translations being applied.
Fix this situation by applying bus translations in the live tree case as
well.
Signed-off-by: Mario Six <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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Now this driver is used across stm32f4, stm32f7 and stm32h7
SoCs family, give it a generic name.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.
Cc: Dan Murphy <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.
Cc: Bin Meng <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Philipp Tomsich <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for simple memory fill operation. With large data sizes
it is much faster to use EDMA for memory fill rather than CPU.
Signed-off-by: Tero Kristo <[email protected]>
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omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".
Fix it here by using "&= ~()" to reset a bit.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The omap hsmmc host controller can have the ADMA2 feature. It brings better
read and write throughput.
On most SOC, the capability is read from the hl_hwinfo register. On OMAP3,
DMA support is compiled out.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The ternary operation had the HIGH/LOW values the
wrong way round. Update it to use the correct value.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Add 'Hz' when printing clock frequency in error messages.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
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Correctly allocate hsdk_cgu_clk private data structure using
priv_auto_alloc_size instead of platdata_auto_alloc_size.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
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Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.
Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
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