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Add generic compatible to the GPIO driver for Gen3 SoCs.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add new compatible to the GPIO driver for R8A77995 D3 SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add new compatible to the GPIO driver for R8A77970 V3M SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add PFC tables for R8A77995 D3 SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add PFC tables for R8A77970 V3M SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add clock tables for R8A77995 D3 SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Add clock tables for R8A77970 V3M SoC.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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Fix a copy-paste typo in the clock table entry, s/7795/7796/.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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The .probe_chip function is supposed to probe an i2c device on the bus to
determine whether a device is answering to a particular address.
at91_i2c_probe_chip() did not do anything resembling this and always
returned 0.
It looks as though at91_i2c_probe_chip() was intended to be a .probe
function for the controller, as it was copied-and-pasted to become
at91_i2c_probe() in 0bc8f640a4d7ed.
Removing the at91_i2c_probe_chip() function makes the higher layer
(i2c_probe_chip()) try a zero-length read transfer to test for the
presence of a device instead, which does work.
Signed-off-by: Alan Ott <[email protected]>
Acked-by: Wenyou Yang <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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The driver must wait for TXRDY after each byte is pushed into
the i2c FIFO before pushing the next byte. Previously this was
not done for the first byte, causing a race condition with zeros
sometimes being sent for the next byte (which is typically the
first actual data byte).
Signed-off-by: Alan Ott <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Add some comment describing the purpose of struct members and
functions.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Change meson_i2c_xfer_msg() to return -EREMOTEIO in case of NACK, as
done by other drivers. Also, don't change the return error in
meson_i2c_xfer().
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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The datasheet doesn't specify a suggested timeout and 500ms seems very
long: reduce it to 100ms.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Expand the Kconfig description with hardware features.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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>From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.
Signed-off-by: Stefan Mavrodiev <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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For case when MC is loaded but DPL is not deployed perform MC
object [DPBP, DPIO, DPNI and DPRC] cleanup.
Signed-off-by: Yogesh Gaur <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Existing MC driver framework is based on MC-9.x.x flib. This patch
migrates MC obj (DPBP, DPNI, DPRC, DPMAC etc) to use latest MC flib
which is MC-10.3.0.
Changes introduced due to migration:
1. To get OBJ token, pair of create and open API replaces create APIs
2. Pair of close and destroy APIs replaces destroy APIs
3. For version read, get_version APIs replaces get_attributes APIs
4. dpni_get/reset_statistics APIs replaces dpni_get/set_counter APIs
5. Simplifies struct dpni_cfg and removes dpni_extended_cfg struct
6. Single API dpni_get_buffer_layout/set_buffer_layout replaces
dpni_get_rx/set_rx, tx related, tx_conf_buffer_layout related APIs.
New API takes a queue type as an argument.
7. Similarly dpni_get_queue/set_queue replaces
dpni_get_rx_flow/set_rx_flow , tx_flow related, tx_conf related
APIs
Signed-off-by: Yogesh Gaur <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Reviewed-by: York Sun <[email protected]>
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In Linux, the warning messages are printed out by pr_warn().
We can use Linux-like log functions in tree-wide.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Include necessary headers explicitly without relying on indirect
header inclusion.
<common.h>, <malloc.h> are unneeded.
Signed-off-by: Masahiro Yamada <[email protected]>
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The Linux derived log functions can be used anywhere and easily
turned on/off by CONFIG_LOGLEVEL.
Signed-off-by: Masahiro Yamada <[email protected]>
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This header was renamed to rawnand.h in Linux.
The following is the corresponding commit in Linux.
commit d4092d76a4a4e57b65910899948a83cc8646c5a5
Author: Boris Brezillon <[email protected]>
Date: Fri Aug 4 17:29:10 2017 +0200
mtd: nand: Rename nand.h into rawnand.h
We are planning to share more code between different NAND based
devices (SPI NAND, OneNAND and raw NANDs), but before doing that
we need to move the existing include/linux/mtd/nand.h file into
include/linux/mtd/rawnand.h so we can later create a nand.h header
containing all common structure and function prototypes.
Signed-off-by: Masahiro Yamada <[email protected]>
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This driver is highly dependent on the configuration from denali_dt.c
Please enable CONFIG_NAND_DENALI_DT if you use this driver.
Signed-off-by: Masahiro Yamada <[email protected]>
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denali_setup_data_interface() is always used.
I put __maybe_unused for a temporal use, then forgot to delete it.
Signed-off-by: Masahiro Yamada <[email protected]>
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Commit 72443c7f7d21 ("mtd: cfi: Add support for status register
polling") added a feature check to determine if status register
is available for certain flash chips. The "lower software bits"
register used to determine this feature is not backward compati-
ble. Older flash chips without this feature has reserved value
0xff. Instead of checking "lower software bits" register, use
CFI primary vendor-specific extended query. Since CFI version
1.4, software features can be read from offset 0x53 according to
document AN201168 from Cypress.
Signed-off-by: York Sun <[email protected]>
CC: Marek Vasut <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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These are actually different bits, and since some monitors (Benq BL2420PT)
have modes with different HSYNC and VSYNC polarity, we should set them
independently
Tested on Pine64-LTS with Benq BL2420PT monitor.
Signed-off-by: Vasily Khoruzhick <[email protected]>
Reviewed-by: Anatolij Gustschin <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add support for setting up SimpleFB for LCD display output in DE2
SimpleFB setup code.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
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RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width.
This patch is only used for U-Boot, but not for SPL which will
comes later, maybe after we merge all the common code into a common
file.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add rk3128 pinctrl driver and grf/iomux structure definition.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add rk3128 clock driver and cru structure definition.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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bbt_mirror_descr and bbt_main_descr is defined but not used
when compiling without CONFIG_SYS_NAND_USE_FLASH_BBT set.
Signed-off-by: Sean Nyekjaer <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The capabilities have default values which doesn't reflect the reality
when it concerns the base clock and the mul value. Use a fixe rate
for the gck. 240 MHz is an arbitrary choice, it is a multiple of the
maximum SD clock frequency handle by the controller and it allows to
get a 400 kHz clock for the card initialisation.
Signed-off-by: Ludovic Desroches <[email protected]>
Signed-off-by: Wenyou Yang <[email protected]>
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Differentiate the generic clock source selection value from the parent
clock index to fix the incorrect assignment of the generic clock
source selection.
Signed-off-by: Wenyou Yang <[email protected]>
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To get the same behavior as the Linux driver, instead of selecting
the closest inferior rate, select the closest inferior or superior
rate
Signed-off-by: Ludovic Desroches <[email protected]>
Signed-off-by: Wenyou Yang <[email protected]>
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What the AT91_UTMI depends on SPL_DM isn't right. AT91_UTMI is not
only used in SPL, also in other place, even if SPL_DM isn't enabled.
Signed-off-by: Wenyou Yang <[email protected]>
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MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.
STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr register whereas there
are located into dckcfgr2 registers on STM32F7.
In both registers, bits CK48MSEL and SDMMC1SEL are located at
the same position.
Signed-off-by: Christophe Priouzeau <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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STM32F4 doesn't get rcc.h file, to avoid compilation
issue, migrate RCC related defines from rcc.h to driver
file and remove rcc.h file.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c
Fix also some checkpatch errors/warnings.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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STM32F4 and STM32F7 RCC clock IP are very similar.
Same driver can be used to managed RCC clock for
these 2 SoCs.
Differences between STM32F4 and F7 will be managed using
different compatible string :
_ overdrive clock is only supported by STM32F7
_ different sys_pll_psc parameters can be used between STM32F4
and STM32F7.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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Add a dedicated stm32f7 compatible string to use clk_stm32f7
driver with both STM32F4 and STM32F7 SoCs.
It will be needed to manage differences between these 2 SoCs.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
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AE3XX can not support SD high-speed mode.
SW can work-around by removing HS capibility.
Signed-off-by: Rick Chen <[email protected]>
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Bit of DATA_END and DATA_CRC_OK shall be checked for
returning pass or fail of a request.
Signed-off-by: Rick Chen <[email protected]>
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ftsdc010 support device tree flow.
Signed-off-by: Rick Chen <[email protected]>
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Add nds32_mmc to support ftsdc010 dm flow.
Signed-off-by: Rick Chen <[email protected]>
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