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While the USB HW in the RZ/A is basically the same, there are some
differences from the original versions that were in the SH SoCs.
Signed-off-by: Chris Brandt <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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before relocation pinctrl data BSS is overlapping DT area,
when .data is using uninitialized global variable,
imx6_pinctrl_soc_info. So assign them flags ZERO_OFFSET_VALID
to prevent BSS overlap
Suggested-by: Lokesh Vutla <[email protected]>
Reported-by: Jagan Teki <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Existing FPGA program write is always assume RBF data >= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size >= 4 bytes.
Signed-off-by: Tien Fong Chee <[email protected]>
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This prevents board resets when calling sdp command on boards which have a watchdog.
Signed-off-by: Vincent Prince <[email protected]>
Reviewed-by: Lukasz Majewski <[email protected]>
Reviewed-by: Stefan Agner <[email protected]>
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Increase the buffer length to be just above maximum permissible value
of 128 kiB . This increases the performance of the UMS and alike by a
factor of 2 - 2.5 as the buffers are less fragmented.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Lukasz Majewski <[email protected]>
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Its a valid use case to call ehci_submit_async() with a NULL buffer
with length 0. E.g. from usb_set_configuration().
As invalidate_dcache_range() isn't able to judge if the address
NULL is valid or not (depending on the SoC hardware configuration it
might be valid) do the check in ehci_submit_async() as here we know
that we don't have to invalidate such a buffer.
Signed-off-by: Dirk Behme <[email protected]>
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Currently we check in ehci_shutdown() if ctrl is NULL after
dereferencing it.
Before this we have already dereferenced ctrl, ctrl->hccr,
and ctrl->hcor in ehci_get_portsc_register(), ehci_submit_root(),
and hci_common_init().
A better approach is to already check ctrl, ctrl->hccr, and ctrl->hcor
during the initialization in ehci_register() and usb_lowlevel_init()
and signal an error here via the return code.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add firmware V3, firmware loader and XHCI glue for the Renesas R-Car
Gen3 SoCs XHCI controller. Thus far only the R-Car Gen3 R8A7795 ES2.0+
and R8A7796 are supported.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Bin Meng <[email protected]>
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Commit 9000eddbae0d ("drivers/usb/ehci: Use platform-specific accessors")
broke USB 2.0 on big-endian platforms because for them writel/readl()
does automatic conversion of BE data to LE.
Proper implementation requires to use "raw" variant of these accessors
which read/write data without messing with endianess.
While at it replace cpu_to_be32() to be32_to_cpu() in readl() to
keep sane semantics.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Marek Vasut <[email protected]>
Reported-by: Vladimir Boroda <[email protected]>
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The RK3399 has a total of 9 I2C controllers. To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.
For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.
Signed-off-by: Philipp Tomsich <[email protected]>
Tested-by: Klaus Goger <[email protected]>
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The RK3399 clk driver still has a left-over use of extract_bits, which
can be replaced by using bitfield_extract from include/bitfield.h.
This rewrites the invocation to use the shared function.
Signed-off-by: Philipp Tomsich <[email protected]>
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The HSDK can manage some pins via CREG registers block.
Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
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fix typo
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Using priv for new sysreset driver binding.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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After applying the merged sysreset driver, there are build failures
due to an out-of-sync Makefile. This updates drivers/sysreset/Makefile
to address these build failures.
Signed-off-by: Philipp Tomsich <[email protected]>
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Use a common driver for all Rockchip SOC instead of one for each SoC.
Use driver_data for reg offset.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Signed-off-by: Sean Nyekjaer <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The dra7xx series of SOCs contain a temperature sensor and an
associated analog-to-digital converter (ADC) which produces
an output which is proportional to the SOC temperature.
Add support for this temperature sensor.
Signed-off-by: Faiz Abbas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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fix typo
Signed-off-by: Heinrich Schuchardt <[email protected]>
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kmem_cache_destroy calls free which checks for NULL.
Problem was indicated by coccinelle.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add a driver for the I2C controller available on Amlogic Meson SoCs.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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Add support for S35392A RTC. The driver supports both U-Boot driver
models.
Signed-off-by: Nandor Han <[email protected]>
Signed-off-by: Martyn Welch <[email protected]>
Cc: Heiko Schocher <[email protected]>
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Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.
Signed-off-by: Ian Ray <[email protected]>
Signed-off-by: Martyn Welch <[email protected]>
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Add missing parts for i.MX53 PWM support
Acked-by: Nandor Han <[email protected]>
Signed-off-by: Martyn Welch <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Tweak the i2c transfer to work for devices that want to read data
without addressing a register.
Signed-off-by: Nandor Han <[email protected]>
Signed-off-by: Martyn Welch <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Stefano Babic <[email protected]>
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This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.
Signed-off-by: Minghuan Lian <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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In U-boot, serial_tstc was use to determine is there have a character in
serial console that pending for read. If there is no "pending" function
implemented in serial driver, the serial-uclass will return "true(1)"
to indicate there have a character pending to read.
Thus, read a character from nulldev serial will result in continuous
getting -EAGAIN return which might lead system to hang.
This commit is to fix a bug in nulldev serial which implement "pending"
function in nulldev serial to always indicate there is no character in
console that pending for read.
Signed-off-by: Wilson Lee <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Keng Soon Cheah <[email protected]>
Cc: Chen Yee Chew <[email protected]>
Cc: Bin Meng <[email protected]>
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Fix clock division factor initialization for RCC_PLLCFGR
registers.
PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add .getcd callback to check is MMC card is present
Signed-off-by: Patrice Chotard <[email protected]>
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Allow to get and enable MMC related clock
Signed-off-by: Patrice Chotard <[email protected]>
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Allow to get "bus-width" property from device tree
Signed-off-by: Patrice Chotard <[email protected]>
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Convert this driver to driver model.
This driver is also used by VEXPRESS platforms which doesn't
use driver model.
Tested on STM32F746 and STM32F769 platforms.
Signed-off-by: Christophe Priouzeau <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
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Update arm_pl180_mmci_init() prototype by adding struct mmc**
param. This is needed before converting this driver to driver model
in order to use arm_pl180_mmci_init() in driver model and in none
driver model implementation
Signed-off-by: Patrice Chotard <[email protected]>
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This option provides better performance and should really always be
enabled. Make this be default y.
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Jeroen Hofstee <[email protected]>
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The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY.
The PHY acts as a generic PHY but needs a slight configuration right
before it's configuration.
Signed-off-by: Neil Armstrong <[email protected]>
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Add the Amlogic Meson GXL pinctrl support based on the GXBB driver and
the synchronized DTS from Linux 4.13.5
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Beniamino Galvani <[email protected]>
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This currently causes a warning in sandbox and will not do the right
thing:
drivers/core/read.c: In function ‘dev_read_addr_ptr’:
drivers/core/read.c:64:44: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
Use map_sysmem() which is the correct way to convert an address to a
pointer.
Fixes: c131c8bca8 (dm: core: add dev_read_addr_ptr())
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
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This makes the initial changes need to support the
a38x series of SOCs. It adds the device-tree identifier
as well as changing the board_support function to take
the IO address designated by device-tree.
Signed-off-by: Jon Nettleton <[email protected]>
[baruch: use fdt_addr_t; update 37xx and 8K implementations]
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Increase size PCI memory mapping from 32MiB to 128MiB.
Signed-off-by: VlaoMao <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Value provided in MC_MEM_SIZE_ENV_VAR is in hex. Use 16 as base
in simple_strtoul.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Currently the chipselect used to identify the corresponding NAND chip
is stored at the controller and only set during fsl_ifc_chip_init().
This way, only the last NAND chip is working, as the previous value
of cs_nand gets overwritten.
In order to solve this issue the chipselect is computed on demand by
evaluating the bank variable. Thus, the correct chipselect for each
NAND chip operation is used.
Tested on hardware with two NAND chips connected to the IFC
controller.
Signed-off-by: Kurt Kanzenbach <[email protected]>
Acked-by: Scott Wood <[email protected]>
[YS: reformatted commit message]
Reviewed-by: York Sun <[email protected]>
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The zero value returned from qbman_swp_acquire() is an error
condition meaning no free buffer for allocation.
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Kushwaha Prabhakar <[email protected]>
[YS: revised commit message]
Reviewed-by: York Sun <[email protected]>
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Only the H3/H5 SoCs have an internal PHY and its related clock and
reset controls.
Use an #ifdef to guard the internal PHY control code block so it
can be built for other SoCs, such as the A83T or A64.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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due misnaming of CONFIG_SUN4I_EMAC in include/configs/sunxi-common.h,
likely missed in:
commit 3146f0c017df ("Move PHYLIB to Kconfig")
Signed-off-by: Artturi Alm <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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