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MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.
Signed-off-by: Stefan Chulski <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Nadav Haklai <[email protected]>
Reviewed-by: Igal Liberman <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.
Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.
Signed-off-by: Stefan Chulski <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Nadav Haklai <[email protected]>
Reviewed-by: Igal Liberman <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.
Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.
Signed-off-by: Stefan Chulski <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Igal Liberman <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.
Signed-off-by: Stefan Chulski <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Igal Liberman <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.
Issue:
Wrong base address is assigned to MDIO interface during probe.
Fix:
Get MDIO address from PHY handler parent base address.
This should be refined in the future when MDIO driver is implemented.
Signed-off-by: Stefan Chulski <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Igal Liberman <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.
Signed-off-by: Stefan Chulski <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Reviewed-by: Igal Liberman <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
it should return earlier without executing dpbp_exit().
Signed-off-by: Santan Kumar <[email protected]>
Acked-by: Priyanka Jain <[email protected]>
Acked-by: Yogesh Narayan Gaur <[email protected]>
Reviewed-by: York Sun <[email protected]>
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We shouldn't always change the status to okay. There could be
situations that the esdhc is intentionally disabled in the device
tree.
Signed-off-by: Li Yang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.
Signed-off-by: Hou Zhiqiang <[email protected]>
[YS: Revise subject and commit message]
Reviewed-by: York Sun <[email protected]>
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Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.
Signed-off-by: York Sun <[email protected]>
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The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Add missing probe function to the device driver to active a device.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Add the print message to tell us why the erase operation doesn't work.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This adds support for Macronix flash MX25U6435F (device ID 0xc22537).
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The environment variable "disable_giga" can now be used to disable
1000baseTx on the Micrel's KSZ9031.
Signed-off-by: Sebastien Bourdelin <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Added the AFE (Analog Front End) settings for stability to the
Broadcom Cygnus phy. This improves the time take to perform
auto negotiation.
Signed-off-by: Arun Parameswaran <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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move to Kconfig:
CONFIG_BCM_SF2_ETH
CONFIG_BCM_SF2_ETH_DEFAULT_PORT
CONFIG_BCM_SF2_ETH_GMAC
Also modified defconfigs of all platforms that use these configs.
Signed-off-by: Suji Velupillai <[email protected]>
Tested-by: Suji Velupillai <[email protected]>
Reviewed-by: JD Zheng <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
Signed-off-by: Steve Rae <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The correct option is PHY_MICREL_KSZ90X1, but some configs still
select the 9021 and 9031 options, which are deprecated.
Signed-off-by: Alexandru Gagniuc <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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There should be no longer be any ksz9000 users that pick up the PHY
driver from ksz8xxx, so remove ksz9000 remnants from there.
Signed-off-by: Alexandru Gagniuc <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.
As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.
To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.
Signed-off-by: Alexandru Gagniuc <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Signed-off-by: Alexandru Gagniuc <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Don't wait forever.
Pass errors back to the caller.
Signed-off-by: Joe Hershberger <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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The register constants don't use the exact names that are used in the
TRM, so add comments that use the exact names so that it is clear what
register is being referred to.
https://www.atheros-drivers.com/qualcomm-atheros-datasheets-for-AR9331.html
Signed-off-by: Joe Hershberger <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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After upgrading to GCC 7.1, the duplicate const specifies in the
r8152 driver trigger the following build warnings with buildman
(observed on a 'buildman rockchip' test)::
../drivers/usb/eth/r8152.c:62:35: warning: duplicate 'const' declaration specifier [-Wduplicate-decl-specifier]
static const struct r8152_version const r8152_versions[] = {
^~~~~
This commit fixes these by removing the duplicate 'const' specifier
from the declarations.
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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phy_device_create(..) sets the addr of phy_device with a sane value.
There is no need overwrite it.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Hannes Schmelzer <[email protected]>
Tested-by: Hannes Schmelzer <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Signed-off-by: Eric Gao <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Add rk3288 soc specific driver for mipi dsi.
Signed-off-by: Eric Gao <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
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Add Makefile item for soc specific driver for rk3399 mipi dsi.
Signed-off-by: Eric Gao <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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To compatible with different rockchip soc, we split the mipi dirver into
common and soc specific parts, and all the soc share the common
functions from common driver part.
Signed-off-by: Eric Gao <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
[agust: fix build breakage and warnings]
Signed-off-by: Anatolij Gustschin <[email protected]>
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This is not used in U-Boot.
Signed-off-by: Bin Meng <[email protected]>
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This is not used in U-Boot.
Signed-off-by: Bin Meng <[email protected]>
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This is not used in U-Boot.
Signed-off-by: Bin Meng <[email protected]>
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This is not used in U-Boot.
Signed-off-by: Bin Meng <[email protected]>
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Xilinx changes for v2017.09
Zynq:
- Add Z-Turn board support
fpga:
- Remove intermediate buffer from code
Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver
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ahci_probe_scsi() now takes a 'base' argument, and there is an API
that prepares base address for us: ahci_probe_scsi_pci().
Reported-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Bin Meng <[email protected]>
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Add support for enabling and disabling the clock using the clock
framework based on the content of OF instead of doing it manually
in the board file.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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The order of parameters passed to the phy_connect() was wrong.
Moreover, only PHY address 0 was used. Replace this with code
capable of detecting the PHY address.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Add support for probing the RAVB Ethernet block from device tree.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Since we now have clock driver on the RCar Gen3 , obtain the clock
configuration using the clock framework functions. In case this
fails, fall back to the original code for pulling the clock config
directly out of OF.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Convert the SH Serial to Kconfig using tools/moveconfig.py tool
and a bit of manual adjustment to cater for failed conversions.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs .
This driver allows reading out the clock configuration set by
previous boot stages and enabling and disabling clock using
the MSTP registers. Setting clock is not supported thus far.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
include/configs/ls1046aqds.h
include/configs/ls1046ardb.h
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Dont use local temporary buffer for printing out the
info instead use directly from memroy. This fixes the
issue of stack corruprion due to local buffer overflow.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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These macros and one variable is not used anywhere that's why
they should be removed.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Dont panic incase of mmio write/read failures instead return
error and let the peripheral driver take care of clock get
and set failures.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for CCF, this CCF reads the ref clocks
from dt and checks all the required clock control
registers for its source , divisors and calculates
the clock from them. This supports clock and set
functions.
Panic when read/write fails.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update SVR as per the SOC document.
-LS2081A: 0x870919 -> 0x870918
-LS2041A: 0x870915 -> 0x870914
Signed-off-by: Santan Kumar <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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