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The rkpwm reg order has fixed by below patch:
e3ef41d rockchip: pwm: fix the register layout for the PWM controller
We need to correct the parameter order for pwm_set_config() to make
the pwm regulator works correctly.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This reverts TXCLK toggling that was accidently dropped while reworking
commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the gmac
ethernet interface"). So the TX clock is enabled and we can use
GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled
(!PINTRL_FULL).
Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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We should not handle this pin explicitly from pinctrl. GMAC driver takes
care of it by using a "reset-gpio" in the DT.
This commit removes pull up for GPIO4B0.
Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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This changes the rockchip-efuse driver to use dev_read_addr instead of
devfdt_get_addr.
Signed-off-by: Philipp Tomsich <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
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STM32F7 and H7 shared the same SDRAM control block.
On STM32H7 few control bits has been added.
The current driver need some minor adaptation as FMC block
enable/disable for H7.
Signed-off-by: Patrice Chotard <[email protected]>
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FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some bank1 registers must be
configured.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..().
This will allow drivers to support a live device tree.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC
For STM32F7, FMC block base address is 0xA0000000, but SDRAM
registers are located at offset 0x140 inside FMC block.
Update the stm32_fmc_regs fields with all FMC registers
to map SDRAM registers at the right address.
These additionals registers will be used later.
Signed-off-by: Patrice Chotard <[email protected]>
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Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c
This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Vikas Manocha <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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Replace proprietary clock_get() by clk_get_rate()
The stm32_qspi is now "generic" and can be used
by other STM32 SoCs.
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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Replace proprietary clock_get() by clk_get_rate()
The stm32x7 serial driver is now "generic" and can be used
by other STM32 SoCs.
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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This allow to remove include/dm/platform_data/serial_stm32x7.h
which was included in the past by stm32x7 driver and by
stm32f746-disco.c board file.
Since patch 42bf5e7c27 "serial: stm32f7: add device tree support"
this file is no more needed in board file.
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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clean the code by removing unused enums, structs and
defines related to clocks
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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Add clock framework .get_rate callback.
This step will allow to convert all drivers which was using
proprietary clock_get() to use clock framework .get_rate().
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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Retrieve RCC base address from DT, this will prepare
the ground for future STM32 SoCs support.
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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Also remove its declaration from stm32.h which
is no more needed.
Signed-off-by: Patrice Chotard <[email protected]>
Acked-by: Vikas MANOCHA <[email protected]>
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This commit adds GPIO support to the Amlogic Meson pin controller
driver, based on code from Linux kernel.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Beniamino Galvani <[email protected]>
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It has been a while since ARM Trusted Firmware supported UniPhier SoC
family. U-Boot SPL was intended as a temporary loader that runs in
secure world. It is a maintenance headache to support two different
boot mechanisms. Secure firmware is realm of ARM Trusted Firmware
and now U-Boot only serves as a non-secure boot loader for UniPhier
ARMv8 SoCs.
Signed-off-by: Masahiro Yamada <[email protected]>
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Add FPGA driver support for Arria 10.
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
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Enable FPGA driver build for Arria 10 SPL because FPGA driver is
needed by Arria 10 SPL to configure and getting DDR up before
loading U-boot into DDR and booting from there.
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
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This converts the following to Kconfig:
CONFIG_FPGA_SOCFPGA
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
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Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
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This missing dependency has probably remained under the radar because
MTD_PARTITIONS is still whitelisted.
Signed-off-by: Karl Beldan <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Remove the ARCH_SUNXI dependency on selection of RBTREE.
Cc: Boris Brezillon <[email protected]>
Cc: Maxime Ripard <[email protected]>
Cc: Jagan Teki <[email protected]>
Signed-off-by: Karl Beldan <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Pasting longer lines into the U-Boot console prompt sometimes leads to
characters missing. One problem here is the small 16-byte FIFO of the
legacy NS16550 UART, e.g. on x86 platforms.
This patch now introduces a Kconfig option to enable RX interrupt
buffer support for NS16550 style UARTs. With this option enabled, I was
able paste really long lines into the U-Boot console, without any
characters missing.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
[trini: Guard ns16550_serial_remove with
CONFIG_IS_ENABLED(SERIAL_PRESENT) to match struct assignment]
Signed-off-by: Tom Rini <[email protected]>
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commit 2eb48ff7a210d ("powerpc, 8260: remove support for mpc8260")
removed support for 8260 CPU.
This patch remove some remainders.
Signed-off-by: Christophe Leroy <[email protected]>
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Add missing .h and add missing declarations in .h
Declare local functions as static. Make interrupt_init_cpu function
signatures consistent with how decrementer_count is declared.
Based on warnings reported by 'make C=2'
Signed-off-by: Christophe Leroy <[email protected]>
[trini: drop cpu_init_f as 8xx/83xx are different from the rest, rework
interrupt_init_cpu/decrementer_count]
Signed-off-by: Tom Rini <[email protected]>
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DTB is encoded in big endian. When we retrieve property values,
we need to use fdt32_to_cpu (aka be32_to_cpu) for endian conversion.
This is a bit error-prone, but sparse is useful to detect endian
mismatch.
We need to use (fdt32_t *) instead of (u32 *) for a pointer of a
property value. Otherwise sparse warns "cast to restricted __be32".
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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get_enable should be able to return error values. Hence change
the return type to integer.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Change get_enable return type to int so errors can be returned.
Signed-off-by: Keerthy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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According to MMC spec, the write_counter is 4-byte length,
use 'int' instead of 'long' type for the 'long' is not 4-byte
in 64 bit CPU.
Signed-off-by: Jason Zhu <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
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Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.
This change is also coherent with the structure in kernel.
Signed-off-by: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
CC: Akshay Bhat <[email protected]>
CC: Ken Lin <[email protected]>
CC: Marek Vasut <[email protected]>
CC: Heiko Schocher <[email protected]>
CC: "Sébastien Szymanski" <[email protected]>
CC: Christian Gmeiner <[email protected]>
CC: Stefan Roese <[email protected]>
CC: Patrick Bruenn <[email protected]>
CC: Troy Kisky <[email protected]>
CC: Nikita Kiryanov <[email protected]>
CC: Otavio Salvador <[email protected]>
CC: "Eric Bénard" <[email protected]>
CC: Jagan Teki <[email protected]>
CC: Ye Li <[email protected]>
CC: Peng Fan <[email protected]>
CC: Adrian Alonso <[email protected]>
CC: Alison Wang <[email protected]>
CC: Tim Harvey <[email protected]>
CC: Martin Donnelly <[email protected]>
CC: Marcin Niestroj <[email protected]>
CC: Lukasz Majewski <[email protected]>
CC: Adam Ford <[email protected]>
CC: "Albert ARIBAUD (3ADEV)" <[email protected]>
CC: Boris Brezillon <[email protected]>
CC: Soeren Moch <[email protected]>
CC: Richard Hu <[email protected]>
CC: Wig Cheng <[email protected]>
CC: Vanessa Maegima <[email protected]>
CC: Max Krummenacher <[email protected]>
CC: Stefan Agner <[email protected]>
CC: Markus Niebel <[email protected]>
CC: Breno Lima <[email protected]>
CC: Francesco Montefoschi <[email protected]>
CC: Jaehoon Chung <[email protected]>
CC: Scott Wood <[email protected]>
CC: Joe Hershberger <[email protected]>
CC: Anatolij Gustschin <[email protected]>
CC: Simon Glass <[email protected]>
CC: "Andrew F. Davis" <[email protected]>
CC: "Łukasz Majewski" <[email protected]>
CC: Patrice Chotard <[email protected]>
CC: Nobuhiro Iwamatsu <[email protected]>
CC: Hans de Goede <[email protected]>
CC: Masahiro Yamada <[email protected]>
CC: Stephen Warren <[email protected]>
CC: Andre Przywara <[email protected]>
CC: "Álvaro Fernández Rojas" <[email protected]>
CC: York Sun <[email protected]>
CC: Xiaoliang Yang <[email protected]>
CC: Chen-Yu Tsai <[email protected]>
CC: George McCollister <[email protected]>
CC: Sven Ebenfeld <[email protected]>
CC: Filip Brozovic <[email protected]>
CC: Petr Kulhavy <[email protected]>
CC: Eric Nelson <[email protected]>
CC: Bai Ping <[email protected]>
CC: Anson Huang <[email protected]>
CC: Sanchayan Maity <[email protected]>
CC: Lokesh Vutla <[email protected]>
CC: Patrick Delaunay <[email protected]>
CC: Gary Bisson <[email protected]>
CC: Alexander Graf <[email protected]>
CC: [email protected]
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method
to set I/O to 1.8. To boards that does not support vqmmc-supply,
use vs18_enable in fsl_esdhc_cfg. If regulator is supported,
use fixed 1.8V regulator for vqmmc-supply.
Signed-off-by: Peng Fan <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
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Handle vqmmc supply. Some boards have a fixed I/O voltage
at 1.8V for emmc, so the usdhc also needs to be configured
as 1.8V by setting VSELECT bit. The vs18_enable is the one
that used to checking whether setting VSELECT or not in
the driver. So if vqmmc supply is 1.8V, set vs18_enable,
the driver will set VSELECT.
Signed-off-by: Peng Fan <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
the USDHC controller when init.
This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
structure and priv data, so each controller can have different
settings.
We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem
that it will apply to all USDHC controllers and it only set the 1.8V
at init phase. So if user does not select to the eMMC device,
the voltage on the I/O pins are not correct.
Signed-off-by: Peng Fan <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
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Currently the following build error is seen when a board using MMC SPL
is built and the MXS nand driver is also selected:
arch/arm/cpu/armv7/built-in.o: In function `arch_cpu_init':
arch/arm/cpu/armv7/mx6/soc.c:432: undefined reference to 'mxs_dma_init'
On mx6 the only user of mxs_dma_init() is the mxs nand driver, so
move it there.
Signed-off-by: Fabio Estevam <[email protected]>
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