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In the DTS, the addresses are defined relative to the parent bus. We need
to translate them to get the address as seen by the CPU core.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
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commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL")
handles relocation of GD in SPL if spl_init() is called before
board_init_r(). So, uclass_root.next need not be initialized always
and accessing uclass_root.next->prev gives an abort. Update the
uclass_root only if it is available.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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The Xenon SDHCI driver just missed the integration of this patch:
git ID 6d0e34bf
mmc: sdhci: Distinguish between base clock and maximum peripheral frequency
With this patch applied, the SDHCI subsystem complains now with this warning
while probing:
sdhci_setup_cfg: Hardware doesn't specify base clock frequency
This patch fixes this issue, by providing the missing host->max_clk
variable to the SDHCI subsystem.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Hu Ziji <[email protected]>
Cc: Victor Gu <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Stefan Herbrechtsmeier <[email protected]>
Cc: Jaehoon Chung <[email protected]>
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It's redundant to send cmd13 after cmd9 whose response is not R1b. The
card devices will not be busy w/ cmd9.
Signed-off-by: Ziyuan Xu <[email protected]>
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No need to flush cache for command without data.
Signed-off-by: Kevin Liu <[email protected]>
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This patch adds Intel Tangier eMMC/SDHCI driver.
Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI
controller is one of the devices which are *not* on a PCI and, hence,
cannot be enumerated by standard PCI means. This driver, allows for
SDHCI controller on Tangier SoC to work in U-Boot.
Signed-off-by: Vincent Tinelli <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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We don't want pci_mmc to compile every time x86 compiles, only when
there's a platform that needs it. For that reason, we're adding a new
CONFIG_MMC_PCI which platforms can choose to enable.
Suggested-by: Jaehoon Chung <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
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This patch fixup iommu-map property on pci node to have a valid
mapping of requester-id to stream-id. The requester-id to stream-id
mapping is based on PCI-LUT table initialization.
Signed-off-by: Bharat Bhushan <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Layerscape Chasis-2 also uses same PCIe controller as Chasis-3
and have similar PCI-Lut.
Signed-off-by: Bharat Bhushan <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add nand_size() function to move the nand size print into initr_nand().
Remove nand size print from nand_init() to allow other function to call
nand_init() without printing nand size.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add initialization flag to avoid initializing NAND Flash multiple
times, otherwise it will calculate a wrong total size.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS2088A and its variants have different PCIe node than LS2080A.
The compatible string is updated accordingly.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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SOC’s like LS1012A has only one chip select signal for QSPI flash.
Avoid scanning other flash.
Signed-off-by: Suresh Gupta <[email protected]>
Reviewed-by: York Sun <[email protected]>
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MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
So move QSGMII wriop_init_dpmac() to SoC file.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
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In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Minghuan Lian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch allows using i2c commands (e.g. "i2c probe", "i2c md", etc)
without the need to first select the bus number with e.g. "i2c dev 0".
This is the "i2c" command behavior similar to the one from pre DM, where
by default bus 0 was immediately accessible.
Signed-off-by: Lukasz Majewski <[email protected]>
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This patch updates the way in which psc, sscl and ssch I2C parameters are
calculated to be in sync with v4.9 Linux kernel
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c
The previous method was causing several issues:
- The internal I2C frequency (after prescaler) was far above recommended
one (7 - 12 MHz [*]) - the current approach brings better noise suppression
(as stated in Linux commit: SHA1: 84bf2c868f3ca996e5bb)
- The values calculated (psc, sscl and ssch) were far from optimal, which
caused on the test platform (AM57xx) the I2C0 SCL signal low time (Fast
Mode) of ~1.0us (the standard requires > 1.3 us).
[*] for AM57xx TRM SPRUHZ6G, Table 24,7
"HS I2C Register Values for Maximum I2C Bit Rates in I2C F/S, I2C HS Modes"
Signed-off-by: Lukasz Majewski <[email protected]>
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v4.9 Linux release:
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c
recommends to use SCLH=5 and SCLL=7 values.
This patch sets them to default.
Signed-off-by: Lukasz Majewski <[email protected]>
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Normally, this would probably be done by adding devicetree aliases
to the main dtsi file for the lpc32xx and using bus->req_seq instead.
Since we want to have consistent i2c numbering, we cannot force the
bus->req_seq because. If for instance we have 3 buses numbered
from 0 to 2 with i2c0 enabled, i2c1 disabled and i2c2 enabled;
i2c2 can be selected using 'i2c dev 1' and 'i2c dev 2' commands
because a bus can be probed using req_seq or seq interchangeably.
Signed-off-by: Liam Beguin <[email protected]>
Signed-off-by: Sylvain Lemieux <[email protected]>
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Since the lpc32xx i2c driver does not yet support the devicetree bindings,
this structure is also needed by the board file as the hardware description
is done there.
Signed-off-by: Liam Beguin <[email protected]>
Signed-off-by: Sylvain Lemieux <[email protected]>
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Removed note in the LPC32xx I2C driver for DM conversation.
Signed-off-by: Sylvain Lemieux <[email protected]>
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Adding DM specific wrapper functions and definitions.
Signed-off-by: Liam Beguin <[email protected]>
Signed-off-by: Sylvain Lemieux <[email protected]>
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This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.
Signed-off-by: Liam Beguin <[email protected]>
Signed-off-by: Sylvain Lemieux <[email protected]>
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This is part of the prep work for the migration to the driver model.
Signed-off-by: Liam Beguin <[email protected]>
Signed-off-by: Sylvain Lemieux <[email protected]>
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This is part of the prep work for the migration to the driver model.
What used to be the probe function is now called probe_chip.
Signed-off-by: Liam Beguin <[email protected]>
Signed-off-by: Sylvain Lemieux <[email protected]>
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This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack <[email protected]>
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This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device.
Driver code has been mainly extracted from kernel
drivers/reset/sti/reset-stih407.c
Signed-off-by: Patrice Chotard <[email protected]>
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In the description of function pci_match_one_id(), there are some
problems on arguments list and return value description, so correct
them.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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It is sometimes convenient to know how many and/or which resources are
currently loaded into a TPG, e.g. to test is a flush operation succeeded.
Hence, we add a command that lists the resources of a given type currently
loaded into the TPM.
Signed-off-by: Mario Six <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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If we want to load a key into a TPM, we need to know the designated parent
key's handle, so that the TPM is able to insert the key at the correct place in
the key hierarchy.
However, if we want to load a key whose designated parent key we also
previously loaded ourselves, we first need to memorize this parent key's handle
(since the handles for the key are chosen at random when they are inserted into
the TPM). If we are, however, unable to do so, for example if the parent key is
loaded into the TPM during production, and its child key during the actual
boot, we must find a different mechanism to identify the parent key.
To solve this problem, we add a function that allows U-Boot to load a key into
the TPM using their designated parent key's SHA1 hash, and the corresponding
auth data.
Signed-off-by: Mario Six <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).
For this purpose we introduce a new phy-driver, called "Fixed PHY".
Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.
Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).
During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.
Signed-off-by: Hannes Schmelzer <[email protected]>
Signed-off-by: Hannes Schmelzer <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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Fixed cache misaligned issue in the net driver. The issue shows-up when
a call to flush_dcache_range is made with unaligned memory. The memory
must be aligned to ARCH_DMA_MINALIGN.
Signed-off-by: Suji Velupillai <[email protected]>
Tested-by: Suji Velupillai <[email protected]>
Reviewed-by: Arun Parameswaran <[email protected]>
Reviewed-by: JD Zheng <[email protected]>
Reviewed-by: Shamez Kurji <[email protected]>
Signed-off-by: Steve Rae <[email protected]>
Cover Letter:
This series resolves issues specific to the Broadcom SF2 driver:
- fix cache misaligned issue
- convert to Kconfig
END
Acked-by: Joe Hershberger <[email protected]>
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Currently the mac address is programmed directly in _sunxi_emac_eth_init
making it a one time inflexible operation. By moving it into a separate
function, we can now use this more flexibly.
Signed-off-by: Olliver Schinagl <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This replaces legacy arch/arc/lib/timer.c implementation and allows us
to describe ARC Timers in Device Tree. Among other things that way we
may properly inherit Timer's clock from CPU's clock s they really run
synchronously.
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This mainly adds support for some new boards, like the ARMv8 community
boards MACCHIATOBin and ESPRESSBin
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This commit introduces timer driver for ARC.
ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.
This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.
Signed-off-by: Vlad Zakharov <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for fixed link to NETA driver.
This feature requreed for proper support of SFP modules
and onboard connected devices like Ethernet switches
Signed-off-by: Konstantin Porotchkin <[email protected]>
Signed-off-by: Terry Zhou <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Nadav Haklai <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Add ability to use board-specific initialization flow
to NETA driver (for instance Ethernet switch bring-up)
Signed-off-by: Konstantin Porotchkin <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Nadav Haklai <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The USB device should linked to VBUS regulator through "vbus-supply"
DTS property.
This patch adds handling for "vbus-supply" property inside the USB
device entry for turning on the VBUS regulator upon the host adapter probe.
Signed-off-by: Konstantin Porotchkin <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Neta Zur Hershkovits <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Haim Boot <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y
Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin <[email protected]>
Signed-off-by: Rabeeh Khoury <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Neta Zur Hershkovits <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Haim Boot <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.
If SYSCON is not supported, the driver reverts to the old way of getting
the address from the 3rd memory range
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
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In the DTS, the addresses are defined relative to the parent bus. We need
to translate them to get the address as seen by the CPU core.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
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commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL")
handles relocation of GD in SPL if spl_init() is called before
board_init_r(). So, uclass_root.next need not be initialized always
and accessing uclass_root.next->prev gives an abort. Update the
uclass_root only if it is available.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
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The Xenon SDHCI driver just missed the integration of this patch:
git ID 6d0e34bf
mmc: sdhci: Distinguish between base clock and maximum peripheral frequency
With this patch applied, the SDHCI subsystem complains now with this warning
while probing:
sdhci_setup_cfg: Hardware doesn't specify base clock frequency
This patch fixes this issue, by providing the missing host->max_clk
variable to the SDHCI subsystem.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Hu Ziji <[email protected]>
Cc: Victor Gu <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Stefan Herbrechtsmeier <[email protected]>
Cc: Jaehoon Chung <[email protected]>
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It's redundant to send cmd13 after cmd9 whose response is not R1b. The
card devices will not be busy w/ cmd9.
Signed-off-by: Ziyuan Xu <[email protected]>
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No need to flush cache for command without data.
Signed-off-by: Kevin Liu <[email protected]>
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This patch adds Intel Tangier eMMC/SDHCI driver.
Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI
controller is one of the devices which are *not* on a PCI and, hence,
cannot be enumerated by standard PCI means. This driver, allows for
SDHCI controller on Tangier SoC to work in U-Boot.
Signed-off-by: Vincent Tinelli <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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We don't want pci_mmc to compile every time x86 compiles, only when
there's a platform that needs it. For that reason, we're adding a new
CONFIG_MMC_PCI which platforms can choose to enable.
Suggested-by: Jaehoon Chung <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Felipe Balbi <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
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Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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