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Collect a couple of duplicated defines into a single place.
Signed-off-by: Masahiro Yamada <[email protected]>
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Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>.
Replace all include directives for <asm-generic/errno.h> with
<linux/errno.h>.
<asm-generic/...> is supposed to be included from <asm/...> when
arch-headers fall back into generic implementation. Generally, they
should not be directly included from .c files.
Signed-off-by: Masahiro Yamada <[email protected]>
[trini: Add drivers/usb/host/xhci-rockchip.c]
Signed-off-by: Tom Rini <[email protected]>
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Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <[email protected]>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <[email protected]>
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We are supposed to use #include <...> to include headers in the
public include paths. We should use #include "..." only for headers
in local directories.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada <[email protected]>
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This makes functions much simpler.
Signed-off-by: Masahiro Yamada <[email protected]>
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The remove callbacks of EHCI drivers are often just a wrapper of
ehci_deregister.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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For vidconsole_post_probe(), it is common coding style to let a
probe method return the value of a register function.
The others will become simple wrapper functions.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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These functions can be much simpler by squashing lines for immediate
return.
For *_bind() callbacks, they will be a simple wrapper function of an
upper-level bind API.
For mmc_set_{boot_bus_width,part_conf}, they will be a wrapper of
mmc_switch().
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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We cannot call on the CONFIG_CLK based clk_get_rate function unless
CONFIG_CLK is set.
Signed-off-by: Tom Rini <[email protected]>
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To sync the DT binding with Linux, the register base must be taken
from the parent syscon node.
Signed-off-by: Masahiro Yamada <[email protected]>
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Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c)
to the core support file (clk-uniphier-core.c) because I do not want
to repeat the driver boilerplate when I add more clock data.
Signed-off-by: Masahiro Yamada <[email protected]>
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Clarify these clock data are constant.
Signed-off-by: Masahiro Yamada <[email protected]>
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This patch add clk_get_rate for PWM device.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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pmucru is a module like cru which is a clock controller manage some PLL
and module clocks.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add a Kconfig for Rockchip xhci controller.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This patch add support for rockchip dwc3 controller, which corresponding
to the two type-C port on rk3399 evb.
Only support usb2.0 currently for we have not enable the usb3.0 phy
driver and PD(fusb302) driver.
Signed-off-by: MengDongyang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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We consider the grf setting for pwm controller select as the system
operation instead of driver operation, move it to soc init, let's
remove it from pwm driver first.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This patch use clock API instead of hardcode for get pwm clock.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
Fix printf() to debug() nit:
Signed-off-by: Simon Glass <[email protected]>
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This patch add pinctrl driver for rk3399.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Since FSL_QSPI driver still supporting non-dm code
better to move the Kconfig from DM undefined place.
Cc: Stefano Babic <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add PL bitstream dowload support for ZynqMP
Bitstream will be validated by uboot and loaded
to PL by invoking an smc instruction to ATF which route this request to
PMU FW which will take care of loading it to PL
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
^
drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’:
drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
^
This patch is using one variable to do conversion via u32 variable.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add missing Kconfig to fpga subsystem to be able
to add new options.
Signed-off-by: Michal Simek <[email protected]>
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This patch moves flags macro's to respective member position on
spi_flash_params{}, for better readabilty and finding the
respective member macro's easily.
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Mugunthan V N <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash code from header file.
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Mugunthan V N <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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SECT_32K never used anywhere in the code.
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Mugunthan V N <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Make rx mode flags as generic to spi, earlier mode_rx is
maintained separately because of some flash specific code.
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Mugunthan V N <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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e_rd_cmd is maintained separately for fastest read command code,
since the read commands are computed normally this e_rd_cmd
is not required in spi_flash_params table.
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Mugunthan V N <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Fastest read command code look for fastest read command
taking inputs from spi->mode_rx and flags from param table
and controller mode_rx is always been a priority.
Since mode_rx is always set from controller side this optimized
code doesn't require much and this code required exctra overhead like
1) Maintain e_rx_cmd in param table
2) Maintain mode_rx in spi_slave {}
Hence removed this code, and look for read command from normal
spi->mode from spi_slave{} and params->flags
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Mugunthan V N <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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This udelay() was added as an HACK and is no longer required. All
read/write/erase operations work fine even without this delay. Hence,
remove the udelay() call.
Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot.
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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TI QSPI has four 32 bit data registers which can be used to transfer 16
bytes of data at once. The register group QSPI_SPI_DATA_REG_3,
QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is
treated as a single 128-bit word for shifting data in and out. The bit
at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out
in case of 128 bit transfer mode. Therefore the first byte to be written
to flash should be at QSPI_SPI_DATA_REG_3[31-25] position.
Instead of writing 1 byte at a time when interacting with SPI NOR flash,
make use of all the four registers so that 16 bytes can be transferred
in one go.
With this patch, the flash write speed increases from ~250KBs/ to
~650KB/s on DRA74 EVM.
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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During spi transfer, for example:
sspi 1:1.0 8 ff
the rx_len values will be:
rx_len = 0
rx_len = 4294967295
This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo
Signed-off-by: Lad, Prabhakar <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Siva Durga Prasad Paladugu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Provide a trivial syscon driver matching the generic "syscon" compatible
string, allowing for simple system controllers to be used without a
custom driver just as in Linux.
Signed-off-by: Paul Burton <[email protected]>
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Device model drivers have previously been matched to FDT nodes by virtue
of being the first driver in the driver list to be compatible with the
node. This ignores the fact that compatible strings in the device tree
are listed in order of priority - that is, if we have a node with 2
compatible strings & a driver that matches each then we should always
probe the driver that matches the first compatible string.
Fix this by looping through the compatible strings for a node when
attempting to bind it in lists_bind_fdt and checking each driver for
a match of the first string, then each driver for a match of the second
string etc. Effectively this inverts the loops over compatible strings &
drivers.
Signed-off-by: Paul Burton <[email protected]>
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The regmap_read & regmap_write functions were previously declared in
regmap.h but not implemented anywhere. The regmap implementation &
commit message of 6f98b7504f70 ("dm: Add support for register maps
(regmap)") indicate that only memory mapped accesses are supported for
now, so providing simple implementations of regmap_read & regmap_write
is trivial. The access size is presumed to be 4 bytes & endianness is
presumed native, which are the defaults for the regmap code in Linux.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mismatched pointer &
integer sizes and then failing to keep track of addresses correctly at
runtime.
Fix the driver for 64 bit systems by using unsigned longs in place of
the previously used 32 bit integers.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Reading the PCI BAR & converting the result to a physical address is not
safe across all architectures. For example on MIPS the virtual:physical
mapping is not 1:1, so we cannot directly make use of the physical
address.
Use the more generic BAR-mapping function dm_pci_map_bar to discover the
MMIO base address, which should work across architectures.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In pci_uclass_pre_probe an attempt is made to detect whether the parent
of a device is a PCI device and that the device is thus a bridge. This
was being done by checking whether the parent of the device is of the
UCLASS_ROOT class. This causes problems if the PCI controller is a child
of some other non-PCI node, for example a simple-bus node.
For example, if the device tree contains something like the following
then pci_uclass_pre_probe would incorrectly believe that the PCI
controller is a bridge, with a PCI parent:
/ {
some_child {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <>;
pci_controller: pci@10000000 {
compatible = "my-pci-controller";
device_type = "pci";
reg = <0x10000000 0x2000000>;
};
};
};
Avoid this incorrect detection of bridges by instead checking whether
the parent devices class is UCLASS_PCI and treating a device as a bridge
when this is true, making use of device_is_on_pci_bus to perform this
test.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Previously ns16550 compatible UARTs probed via device tree have needed
their device tree nodes to contain a clock-frequency property. An
alternative to this commonly used with Linux is to reference a clock via
a phandle. This patch allows U-Boot to support that, retrieving the
clock frequency by probing the appropriate clock device.
For example, a system might choose to provide the UART base clock as a
reference to a clock common to multiple devices:
sys_clk: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <10000000>;
};
uart0: uart@10000000 {
compatible = "ns16550a";
reg = <0x10000000 0x1000>;
clocks = <&sys_clk>;
};
uart1: uart@10000000 {
compatible = "ns16550a";
reg = <0x10001000 0x1000>;
clocks = <&sys_clk>;
};
This removes the need for the frequency information to be duplicated in
multiple nodes and allows the device tree to be more descriptive of the
system.
Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]>
Reviewed-by: Paul Burton <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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out_be32 and in_be32 are actually #defined to little endian
writel/readl in arch/microblaze.
Just use __raw_writel/readl instead. That is also what is used
in the Linux kernel driver for this IP block
Tested on MIPSfpga. Can tftp a kernel.
Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]>
Reviewed-by: Paul Burton <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Virtual to physical mapping isn't necessarily 1:1 for all architectures
Using ioremap_nocache allows for the arch code to translate the
physical address to a virtual address.
Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]>
Reviewed-by: Paul Burton <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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