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When DTO interrupt occurred, there are any remaining data still in FIFO
due to RX FIFO threshold is larger than remaining data. It also
causes that dwmmc didn't trigger RXDR interrupt, so is TX.
It's responsibility of driver to read remaining bytes on seeing DTO
interrupt.
Signed-off-by: Jacob Chen <[email protected]>
Signed-off-by: Ziyuan Xu <[email protected]>
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Add the programmable clock mode for the clock generator.
Signed-off-by: Wenyou Yang <[email protected]>
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To SD, there is no erase group, then the value erase_grp_size
will be default 1. When erasing SD blocks, the blocks will be
erased one by one, which is time consuming.
We use AU_SIZE as a group to speed up the erasing.
Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB.
`time mmc erase 0x100000 0x2000`
time: 44.856 seconds (before optimization)
time: 0.335 seconds (after optimization)
Signed-off-by: Peng Fan <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Stefan Wahren <[email protected]>
Cc: Clemens Gruber <[email protected]>
Cc: Kever Yang <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Stephen Warren <[email protected]>
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Add function to read SD_STATUS information.
According to the information, get erase_timeout/erase_size/erase_offset.
Add a structure sd_ssr to include the erase related information.
Signed-off-by: Peng Fan <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Stefan Wahren <[email protected]>
Cc: Clemens Gruber <[email protected]>
Cc: Kever Yang <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Stephen Warren <[email protected]>
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No need for per-SoC adjustment for this parameter. It should be
determined by the slowest hardware. Currently, no board overrides
this CONFIG, so 3.2 sec is large enough. (If not, we can make it
even larger.)
Signed-off-by: Masahiro Yamada <[email protected]>
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This CONFIG is not configurable since it is not guarded by #ifndef.
Nobody has complained about that, so there is no need to keep it as
a CONFIG option.
Signed-off-by: Masahiro Yamada <[email protected]>
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If CONFIG_BLK is enabled, add_sdhci() is never called. Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.
Signed-off-by: Masahiro Yamada <[email protected]>
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If CONFIG_BLK is enabled, add_sdhci() is never called. Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.
Signed-off-by: Masahiro Yamada <[email protected]>
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"Hardware doesn't specify base clock frequency" may not be only the
error case of sdhci_setup_cfg(). It is better to print this where
the corresponding error is triggered.
Signed-off-by: Masahiro Yamada <[email protected]>
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If CONFIG_BLK is enabled, add_sdhci() is never called.
So, sdhci_reset() is not called, either. This is a problem for
my board as it needs the reset to start from a sane state.
Move the add_sdhci() call to sdhci_init(), which is visited
by both of the with/without CONFIG_BLK cases.
Signed-off-by: Masahiro Yamada <[email protected]>
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Add pin-mux support for UniPhier sLD3 SoC.
Signed-off-by: Masahiro Yamada <[email protected]>
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On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit
wide on sLD3 SoC. Support it for the sLD3 pinctrl driver.
Signed-off-by: Masahiro Yamada <[email protected]>
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With sunxi-musb musb_lowlevel_init() can fail when a charger; or no cable
is plugged into the otg port.
To avoid leaking the struct musb allocated by musb_init_controller()
on repeated musb_usb_probe() calls, we were caching its result.
But musb_init_controller() does more, such as calling sunxi_musb_init()
which enables the clocks.
Not calling sunxi_musb_init() causes the musb controller to stop working
after a "usb reset" since that calls musb_usb_remove() which disables the
clocks.
This commit fixes this by removing the caching of the struct returned
from musb_init_controller(), it replaces this by free-ing the allocated
memory in musb_usb_remove() and calling musb_usb_remove() on
musb_usb_probe() errors to ensure proper cleanup.
While at it also make musb_usb_probe() and musb_usb_remove() static.
Signed-off-by: Hans de Goede <[email protected]>
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The Linux kernel musb driver expects VBUS to be off while initializing
musb. Having it on results in a repeating string of warnings, followed
by an unusable peripheral. The peripheral is only usable after
physically removing the OTG adapter, letting musb reset its state.
This partially reverts commit c9f8947e6604 ("sunxi: usb-phy: Never
power off the usb ports")
Signed-off-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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When cold-booting the ldoio0/1 regulators are always off / the
gpios are always at tristate. But when re-booting from android these
are sometimes on. Disable them at axp_init time (iow as early as possible)
to remove this difference between a cold boot and a reboot.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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At present TPL uses the same options as SPL support. In a few cases the board
config enables or disables the SPL options depending on whether
CONFIG_TPL_BUILD is defined.
With the move to Kconfig, options are determined for the whole build and
(without a hack like an #undef in a header file) cannot be controlled in this
way.
Create new TPL options for these and update users. This will allow Kconfig
conversion to proceed for these boards.
Signed-off-by: Simon Glass <[email protected]>
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When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error
that temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Debug server feature has been dropped from roadmap.
Signed-off-by: York Sun <[email protected]>
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DDR controller 5.2.1 has this erratum A008511 partially fixed.
The workaround needs to be adjusted to take advantage of Vref
training. This patch enables the training and force output
enable to be off.
Erratum A009803 requires the controller to be idel before enabling
address parity. It was combined with workaround for A008511. With
new A008511 flow, this flow needs to be changed to enabling
data init (D_INIT) after the address parity is enabled.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Shengzhou Liu <[email protected]>
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32 more debug registers are added for newer DDR controllers.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Shengzhou Liu <[email protected]>
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The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
Reviewed-by: York Sun <[email protected]>
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These macros are only referenced in pinctrl-uniphier-core.c, so
they need not reside in a header file.
Signed-off-by: Masahiro Yamada <[email protected]>
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This is needed to get access to UniPhier System Bus (external bus).
Signed-off-by: Masahiro Yamada <[email protected]>
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This is the state-of-the-art MMC driver implementation.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver has not been converted to Driver Model, and it is an
obstacle to migrate other block device drivers. Remove it for now.
The UniPhier SoCs already use a DM-based EHCI driver, so now
ARCH_UNIPHIER can select DM_USB.
These two changes must be done atomically because removing the
legacy driver causes a build error.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Since the 'clk_client.h' doesn't exist, it should be 'clk.h'.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The special handling of the chip address and register address must only
happen before we send the data buffer, otherwise we will end up
inserting both of these every 32 bytes.
Signed-off-by: John Keeping <[email protected]>
Acked-by: Simon Glass <[email protected]>
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There is no point in writing intermediate values to the txdata
registers.
Also add padding to the debug logging to make it easier to read when
there are leading zeroes.
Signed-off-by: John Keeping <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Make it clear that we are using the same value in two adjacent lines.
Signed-off-by: John Keeping <[email protected]>
Acked-by: Simon Glass <[email protected]>
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A previous patch (net: asix: fix operation without eeprom) added a
two-byte shift to the packet buffer when receiving a packet on the
AX88772B.
This shift was not included when the driver was updated to work with
DriverModel. Testing on a Marvell DB-88F6820-ACM showed that the adapter
was not functioning correctly (EHCI timeouts).
This patch brings the two-byte shift to the DriverModel implementation
of ops->recv (asix_eth_recv).
Testing on the same board, we were able to TFTP a file over and confirm
that the crc32 was correct.
Signed-off-by: Joshua Scott <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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When enabling a fixed regulator, it may take some time to rise to the
correct voltage. If we do not delay here then subsequent operations
will fail.
Signed-off-by: John Keeping <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add a pin controller driver for Meson GXBB adapted from Linux kernel.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In cases where the pins and groups definitions are in a sub-node, as:
uart_a {
mux {
groups = "uart_tx_a", "uart_rx_a";
function = "uart_a";
};
};
pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
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On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.
However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted on to whoever calls
getc() today.
This patch adds detection logic for that case by checking whether the RX pin is
mapped to GPIO15 and disables the mini uart if it is not mapped properly.
That way we can leave the driver enabled in the tree and can determine during
runtime whether serial is usable or not, having a single binary that allows for
uart and non-uart operation.
Signed-off-by: Alexander Graf <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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So far we could only tell the gpio framework that a GPIO was mapped as input or
output, not as alternative function.
This patch adds support for determining whether a function is mapped as
alternative.
Signed-off-by: Alexander Graf <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Currently the command buffer gets allocated with a size of 32 bytes.
This causes warning messages on systems with cache lines bigger than
32 bytes:
CACHE: Misaligned operation at range [9df17a00, 9df17a20]
Define command buffer to be at least 32 bytes, but more if cache
line is bigger.
Signed-off-by: Stefan Agner <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
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Now that nand_info[] is an array of pointers we need to test the
pointer itself rather than using name as a proxy for NULLness.
Fixes: b616d9b0a708eb9 ("nand: Embed mtd_info in struct nand_chip")
Signed-off-by: Scott Wood <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Tony Lindgren <[email protected]>
Acked-by: Tony Lindgren <[email protected]>
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In commit 17cb4b8f327e ("mtd: nand: Add+use mtd_to/from_nand and
nand_get/set_controller_data") the assignment of mtd->priv was removed
but was not replaced. This adds the required nand_set_controller_data()
call.
Signed-off-by: Chris Packham <[email protected]>
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This is very likely to be necessary for normal use cases.
Set its default to 'y' for shorter defconfig files.
Signed-off-by: Masahiro Yamada <[email protected]>
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With this, we can save unnecessary udelay().
Signed-off-by: Masahiro Yamada <[email protected]>
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With the CONFIG_DM_MMC_OPS migration, the .set_ios callback can
return an integer now. Return an appropriate error value rather
than sudden death by BUG().
Signed-off-by: Masahiro Yamada <[email protected]>
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No more reason to define this function above the ops structure.
Move it near the caller. Also, change its return type to void
because it never fails.
Signed-off-by: Masahiro Yamada <[email protected]>
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Catch up with the DM migration.
As struct dm_mmc_ops does not have .init callback, call the init
function directly from the probe function.
Signed-off-by: Masahiro Yamada <[email protected]>
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They are both only referenced in this file.
Signed-off-by: Masahiro Yamada <[email protected]>
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