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Add support to dwmmc for using driver model for MMC operations.
Signed-off-by: Simon Glass <[email protected]>
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The driver model conversion for MMC has moved in small steps. The first step
was to have an MMC device (CONFIG_DM_MMC). The second was to use a child
block device (CONFIG_BLK). The final one is to use driver model for MMC
operations (CONFIG_DM_MMC_OP). Add support for this.
The immediate priority is to make all boards that use DM_MMC also use those
other two options. This will allow them to be removed.
Signed-off-by: Simon Glass <[email protected]>
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Move this code into separate functions so that it can be used from the uclass
also. Add static inline versions for when the option is disabled.
Signed-off-by: Simon Glass <[email protected]>
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Since all Rockchip boards use CONFIG_BLK, we can remove this old code.
Signed-off-by: Simon Glass <[email protected]>
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Rather than having an #ifdef in the main mmc.c file, control this feature
from the Makefile by moving the code into its own file.
Signed-off-by: Simon Glass <[email protected]>
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Rather than having #ifdef in mmc.c, move this code into the legacy file.
Signed-off-by: Simon Glass <[email protected]>
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Rather than having #ifdef in mmc.c, move this code into the uclass file.
Signed-off-by: Simon Glass <[email protected]>
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These private functions are used both in the driver-model implementation and
in the legacy code. Add them to the header.
Signed-off-by: Simon Glass <[email protected]>
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In case of DT boot, don't read default speed and mode for SPI from
CONFIG_*, instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.
Signed-off-by: Vignesh R <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.
Signed-off-by: Vignesh R <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Convert davinci_spi driver so that it complies with SPI DM framework.
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.
Signed-off-by: Vignesh R <[email protected]>
Suggested-by: Simon Glass <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Add support for standard type SCI (without FIFO) port.
Signed-off-by: Yoshinori Sato <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Add Device Tree bindings.
Signed-off-by: Yoshinori Sato <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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MMC core expects (now) valid mmc->dev pointer.
During conversion in commit cffe5d86 not every driver was updated.
This patch fixes crash while accessing MMC on
boards using Qualcomm SDHCI controller.
Signed-off-by: Mateusz Kulikowski <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.
Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.
Cc: Stephen Warren <[email protected]>
Cc: Joe Hershberger <[email protected]>
Signed-off-by: Oleksandr Tymoshenko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit 90b7fc924adf "net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
* dm_gpio_XXX()
* gpio_request_by_name()
But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Beniamino Galvani <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Sjoerd Simons <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Signed-off-by: Anatolij Gustschin <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This seems to give the best performance, so let's use it always.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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We have standard drivers for panels and backlights which can do most of the
work for us. Move the tegra20 LCD driver over to use those instead of custom
code.
This patch includes device tree changes for the nvidia boards. I have only
been able to test seaboard. If this patch is applied, these boards will
also need to be synced with the kernel, and updated to use display-timings:
- colibri
- medcom-wide
- paz00
- tec
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.
For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.
For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Waiting 30 seconds for the hpd to go high seems a bit much, especially
on headless boots. Lowering the timeout to 300ms.
Sending as RFC because frankly i don't know what a sensible timeout is
here, but 30 seconds is clearly not it :)
Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Dropped RFC tag:
Signed-off-by: Simon Glass <[email protected]>
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Otherwise, ocassionally see errors like this:
Flashing sparse image at offset 2078720
Flashing Sparse Image
sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
write_sparse_image: Write failed, block #2181088 [0]
This does not affect the actual writing speed, which is controlled by
the default value:
CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT
It only increases the retries when reading:
SDHCI_INT_STATUS
to avoid the timeout error.
Signed-off-by: Steve Rae <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Tested-by: Masahiro Yamada <[email protected]>
Tested-by: Jaehoon Chung <[email protected]>
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Correcting QSPI disable/unselect CS reset value.
CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8]
This is not causing any issue, but its better
to untouch the reserved bits.
Praneeth Bajjuri <[email protected]>
Signed-off-by: Ravi Babu <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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SPL does not use all of the devices, so we can save some memory
footprint.
Signed-off-by: Masahiro Yamada <[email protected]>
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PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.
Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function. The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.
[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]
Signed-off-by: Masahiro Yamada <[email protected]>
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PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.
However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development. Split it into two dedicated drivers.
Signed-off-by: Masahiro Yamada <[email protected]>
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Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node. This commit allows to migrate to
the new DT structure.
Signed-off-by: Masahiro Yamada <[email protected]>
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This SoC does not support NAND CS1. This place-holder is no longer
necessary.
Signed-off-by: Masahiro Yamada <[email protected]>
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My mistake in the initial support patch.
Signed-off-by: Masahiro Yamada <[email protected]>
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These are pin group names, not function names.
Signed-off-by: Masahiro Yamada <[email protected]>
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Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.
So append "A" to SoC names.
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
external card and reinitialize it.
So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: York Sun <[email protected]>
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When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.
This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.
Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.
Signed-off-by: Peng Fan <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: York Sun <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: York Sun <[email protected]>
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- update fastboot_okay() and fastboot_fail()
This file originally came from upstream code.
While retaining the storage abstraction feature, this is the second
set of the changes required to resync with the
cmd_flash_mmc_sparse_img()
in the file
aboot.c
from
https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1
Signed-off-by: Steve Rae <[email protected]>
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This "session-id" alogrithm is not required, and currently corrupts
the stored image whenever more the one "session" is required.
Signed-off-by: Steve Rae <[email protected]>
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These condition checking are wrong.
Original Author's intention might be "&" instead of "&&".
It can know whether receive or transmit data request with
BIT[4]/BIT[5] of RINTSTS register.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the
OTG ID detection, not set it. When the bit is set, the ACA
Resistance Detection is enabled, which disables the OTG ID
detection, because the internal pull up is off.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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There is a 4 bytes hole between phy_cfg2 and phy_status, fix the
usbnc_regs structure to include the hole.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Fixes NULL terminating issue for usb controller name string by using
sizeof operator.
Signed-off-by: Rajesh Bhagat <[email protected]>
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