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Samsung S6E63M0 controller is found in some OLED panels like one used in
the Samsung Captivate Glide. Currently only DBI C panel is implemented.
Signed-off-by: Ion Agorria <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Sony L4F00430T01 LCD module is found in Samsung Galaxy R. The panel has a
WVGA resolution (480x800) and is setup over SPI, video data comes from RGB.
Signed-off-by: Ion Agorria <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Configure pixel clock and data enable polarity according to panel flags.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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This driver allows using Tegra AES engines within BSEV and BSEA blocks to
encrypt and decrypt data using different AES algorithms.
One use case is allowing u-boot to self update by using the already loaded
AES key in the engine's SBK slot by the bootrom.
Particular care must be taken as chainloaded u-boot's may not have the SBK
slot loaded as the vendor bootloader erases it before leaving it.
Signed-off-by: Ion Agorria <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236
- Add support for STM32 TIMERS and STM32 PWM on STM32MP25
- Add STM32MP13xx SPL and OpTee-OS start support
- Fix header misuse in stm32 reset drivers
- Fix STMicroelectronics spelling
- Fix clk-stm32h7 wrong macros used in register read
- Fix PRE_CON_BUF_ADDR on STM32MP13
- Fix clock identifier passed to struct scmi_clk_parent_set_in
- Fix stm32 reset for STM32F4/F7 and H7
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
- Add STM32MP23 SoC and stm32mp235f-dk board support
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request includes updates for the SoCFPGA platform intended for the 2025.10 release
cycle. The highlights focus on enabling the Power Manager for Agilex5, NAND boot support
enhancements, and various bug fixes and cleanups across SoCFPGA components.
CI:
* https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27221
Summary of changes:
Agilex5 Power Manager:
* Initial driver support and DT bindings are added for the Agilex5 Power Manager, enabling
better power domain control.
NAND Boot Support for Agilex5:
* SPL support for NAND boot is enabled.
* UBI/UBIFS support is configured in defconfigs.
* Memory layout updates (malloc and BSS relocation) ensure proper boot behavior.
Code Quality Improvements:
* Coverity and runtime bug fixes (e.g., jtag_usercode check, sub-device conditionals).
* Several cleanup patches addressing formatting, logic, and initialization issues.
General Maintenance:
* SPDX license tags and header include fixes.
* Device tree updates to limit SPI clock frequency and other minor adjustments.
These contributions come from Alif Zakuan Yuslaimi, Andrew Goodbody, Dinesh Maniyam, Naresh
Kumar Ravulapalli, and Tingting Meng.
This patch set has been tested on Agilex 5 devkit.
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family"
Lukasz Czechowski <[email protected]> says:
This patch series extends the usb_onboard_hub driver to allow for
support of more types of onboard hub devices, and adds the Cypress HX3
hub family.
First patch in the series updates the bind function, so that it no
longer uses hardcoded compatible strings.
Next patch simplifies the code, by removing unnecessary dm_gpio function
call.
Third patch updates the remove function, which allows the prevent issues
with usb devices reenumeration, in case of calling "usb reset". Although
the issue could still occur in case of invalid initial state of reset
gpio, it is minimized with no impact on main usb_hub driver.
Fourth patch extends the driver with support for multiple power
supplies, the same way it is done in kernel driver. Finally, last patch
provides hub data and of_match table entries for Cypress HX3
Link: https://lore.kernel.org/r/20250722-usb_onboard_hub_cypress_hx3-v4-0-91c3ee958c0e@thaumatec.com
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The reset GPIO is obtained during driver probing by the function
devm_gpiod_get_optional, which means the GPIO will be automatically
freed when the device is removed. Because of this, explicit call
to free the reset GPIO in hub remove function is not needed.
To support the Managed device resources, the DEVRES config must
be enabled, otherwise the devres functions fall back to non-managed
variants. Set the necessary dependency to DEVRES in Kconfig.
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Lukasz Czechowski <[email protected]>
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STM32F4/F7 and H7 series doesn't have a clear reset register, so
set_clr field must be set to false.
Fixes: 0994a627c278 ("reset: stm32mp25: add stm32mp25 reset driver")
Signed-off-by: Patrice Chotard <[email protected]>
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Agilex5 FSBL is required to disable the power of unused peripheral SRAM
blocks to reduce power consumption.
Introducing a new power manager driver for Agilex5 which will be called
as part of Agilex5 SPL initialization process.
This driver will read the peripheral handoff data obtained from the
bitstream and will power off the specified peripheral's SRAM from the
handoff data values.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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In socfpga_dtreg_probe it is possible that if mask is 0 then reg will
not be assigned to before first use. Refactor the code slightly to
ensure that reg is always assigned to and remove a piece of duplicated
code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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The function socfpga_get_handoff_size returns an int so make the struct
fields used to accept the return value also an int so that testing for
less than 0 is then valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Smatch reported an issue about the precedence of shift being higher than
mask in clk_get_emac_clk_hz. This turned out to be a misplaced paren in
one of the calculations. Fix this by placing the paren in the same place
as in the other similar calculations in the same function.
Signed-off-by: Andrew Goodbody <[email protected]>
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The for loop in fpgamgr_program_poll_cd will always terminate after a
single pass and so is not necessary. Remove it and all related code and
leave only the code that is effective.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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On STM32MP reference boards, the watchdog is started by a previous
boot stage (e.g. bootrom or secure OS), so the config flag
WATCHDOG_AUTOSTART is not required.
It's preferable to rely on the DT properties "u-boot,autostart" or
"u-boot,noautostart", if needed.
For backward compatibility on defconfigs that are based on SPL,
thus cannot rely on a previous boot stage for starting the
watchdog, enable WATCHDOG_AUTOSTART in their respective defconfig.
The change in stm32mp15_dhsom.config is propagated to:
- configs/stm32mp15_dhcom_basic.config
- configs/stm32mp15_dhcor_basic.config
and then to:
- stm32mp15_dhcom_basic_defconfig
- stm32mp15_dhcom_drc02_basic_defconfig
- stm32mp15_dhcom_pdk2_basic_defconfig
- stm32mp15_dhcom_picoitx_basic_defconfig
- stm32mp15_dhcor_avenger96_basic_defconfig
- stm32mp15_dhcor_basic_defconfig
- stm32mp15_dhcor_drc_compact_basic_defconfig
- stm32mp15_dhcor_testbench_basic_defconfig
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add a mean to check the IWDG status based on the peripheral version.
This is done by either checking the status bit ONF either by updating
the reload register with the same value and check if the reload succeed.
Signed-off-by: Clément Le Goffic <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The optional SMCWD_GET_TIMELEFT command can be used to detect if
the watchdog has already been started.
See the implementation in OP-TEE secure OS [1].
At probe time, check if the watchdog is already started and then
call wdt_set_force_autostart(). This will keep U-Boot pinging the
watchdog even when the property 'u-boot,noautostart' is present.
Link: https://github.com/OP-TEE/optee_os/commit/a7f2d4bd8632 [1]
Signed-off-by: Antonio Borneo <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The watchdog could have been already started by a previous boot
stage (e.g. bootrom or secure OS). U-Boot has to start and kick
the watchdog even when CONFIG_WATCHDOG_AUTOSTART is not enabled
or when the DT property u-boot,noautostart is present.
Add the helper wdt_set_force_autostart() that can be called by the
driver's probe() when it detects that the watchdog has already
been started and is running.
Co-developed-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Andrew Goodbody <[email protected]> says:
Smatch found two issues in bios_emulator, a buffer overflow and missing
parens for a macro. Fix them both.
Link: https://lore.kernel.org/r/[email protected]
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The xorl macro lacked surrounding parens which meant that it could have
unexpected results when used in expressions. Fix this by adding the
surrounding parens to make its use predictable.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Using strcpy to copy a 4 character string into a 4 byte field in a
structure will overflow that field as it writes the terminating \0 into
the following field. Correct this by using memcpy instead.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=394&view=results
- cmd: tlv_eeprom: Minor improvements (Hugo)
- kirkwood: Enable bootstd and other modernization for ib62x0 board
(Tony)
- spi: mvebu: Correct dependencies on MVEBU_A3700_SPI (Tom)
- ddr: marvell: a38x: Fix unsigned issues detected by smatch (Andrew)
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Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
Signed-off-by: Patrice Chotard <[email protected]>
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Smatch reported a warning about a shift macro being used as a mask. Make
the obvious changes to make this register read calculation work the same
as the previous ones.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Commit aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CFF") enables CONFIG_CLK_AUTO_ID, so need to use clk_get_id() to get the
real SCMI CLK ID, otherwise wrong ID is used when set clk parent.
Fixes: aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CCF")
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
be included using "stm32-reset-core.h" and not <stm32-reset-core.h> ,
otherwise the build fails. Fix it.
Fixes: 0994a627c278 ("reset: stm32mp25: add stm32mp25 reset driver")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add support for STM32MP25 SoC.
IPIDR register is used to check the hardware configuration register
when available to gather the number of complementary outputs.
Signed-off-by: Cheick Traore <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-at91 features for the 2025.10 cycle:
This feature set includes the addition of new sama7d65 SoC and a new
board named sama7d65-curiosity.
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Cannot test an unsigned variable to be less than 0, it will always fail.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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A dependency exposed by "make allyesconfig" is that the logic around
this symbol was not quite correct. It needs to depend on ARCH_MVEBU and
ARM64 and then select CLK_MVEBU.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The X-Powers AXP323 is very close sibling to the AXP313A, only that it
adds support for dual-phasing the first two DC/DC converters.
We do not really care about this particular feature, so just add the new
compatible string and tie it to the existing AXP313A support code.
Signed-off-by: Andre Przywara <[email protected]>
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The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.
Signed-off-by: Andre Przywara <[email protected]>
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The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.
Add the values for the primary and secondary pin controller on the A523.
Signed-off-by: Andre Przywara <[email protected]>
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Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.
Signed-off-by: Andre Przywara <[email protected]>
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Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.
Signed-off-by: Andre Przywara <[email protected]>
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The generic name 'EFI' would be more useful for common EFI features. At
present it just refers to the EFI app and stub, which is confusing.
Rename it to EFI_CLIENT
Signed-off-by: Simon Glass <[email protected]>
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- Enhanced e850-96 support
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Add clock support for SAMA7D65
Signed-off-by: Ryan Wanner <[email protected]>
[[email protected]: add Fractional PLL core
output range]
Signed-off-by: Romain Sioen <[email protected]>
[[email protected]: adapt driver to upstream]
Signed-off-by: Varshini Rajendran <[email protected]>
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Update the MAX PLL and master CLK ID to support sama7d65
SoC family.
Signed-off-by: Ryan Wanner <[email protected]>
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The only thing needed from DWC3 glue layer for Exynos850 is to enable
USB clocks. The generic glue layer driver already does that. Add
Exynos850 dwc3 compatible string to enable support for this chip.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Add DM driver for Exynos USB PHY controllers. For now it only supports
Exynos850 SoC. Only UTMI+ (USB 2.0) PHY interface is implemented, as
Exynos850 doesn't support USB 3.0. Only two clocks are used for this
controller:
- phy: bus clock, used for PHY registers access
- ref: PHY reference clock (OSCCLK)
Ported from Linux kernel: drivers/phy/samsung/phy-exynos5-usbdrd.c
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Minkyu Kang <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27149
- Add support for the NXP imx93 frdm board.
- imx93_evk and phycore-imx93 cleanups.
- Convert imx6dl-sielaff to OF_UPSTREAM and fix serial download mode boot.
- Fix crash in imx power-domain.
- Migrate Phytec imx8mm boards to standard boot.
- Fix smatch warnings.
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Neha Malcom Francis <[email protected]> says:
This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.
At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.
The general procedure for triggering BIST on a core is:
1. Power on the core under test following a sequence
2. Trigger the BIST test
3. Reset the core under test following a sequence
BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.
Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603
[1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3] https://lore.kernel.org/all/[email protected]/
Link: https://lore.kernel.org/r/[email protected]
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Instead of strcpy which is unbounded use strlcpy to ensure that the
receiving buffer cannot be overflowed.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis <[email protected]>
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uclass_find_next_device always returns 0, so instead make it a void and
update calling sites.
Signed-off-by: Andrew Goodbody <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.10-rc1 v2
zynqmp:
- Generate fit-dtb.blob all the time
- Simplify power-domain driver bind
zynqmp_mini:
- Remove PSCI_RESET
fpga:
- Improve user feedback in case of FPGA bitstream load failure
misc:
- Fix kernel-doc in gpio zynq and axi_mrmac
spi:
- Revert fix in STIG mode
[trini: Remove CONFIG_FPGA_VERSALPL=y from sandbox due to
sandbox+clang+asan test problem]
Signed-off-by: Tom Rini <[email protected]>
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Local variable ret is declared as unsigned but is used to receive the
return value of functions that return int. ret is then tested for being
negative which must always fail. Change ret to be an int.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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In case of the i.MX8M power-domains (i.MX8MQ, MM, MN) there is only
one power-domain for each device. Therefore the 'id' field in struct
power_domain should always be zero.
Currently if a power-domain is accessed after the initial bind, the
'id' field is left uninitialized. This didn't cause any problems
until the following commits were introduced:
9086b64ca071 ("power-domain: Add support for refcounting (again)")
a785ef24487b ("imx: power-domain: Enable refcounting on imx8mp")
Now the 'id' field gets accessed in the power_domain_off() sequence
and the invalid value causes "Synchronous Abort" failures.
This was observed on a i.MX8MM board when running "usb start" and
then "usb stop".
Fix this issue by setting power_domain->id to '0' in
imx8m_power_domain_of_xlate().
Signed-off-by: Frieder Schrempf <[email protected]>
Fixes: d08a194871fd ("imx: add support for i.MX8MQ power domain controller")
Fixes: 9086b64ca071 ("power-domain: Add support for refcounting (again)")
Reviewed-by: Miquel Raynal <[email protected]>
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CONFIG_IS_ENABLED macro is covering CONFIG_POWER_DOMAIN or
CONFIG_SPL_POWER_DOMAIN Kconfig symbols based on build target which
simplify logic around binding power domain driver.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c75627e92eeaffedf0f7e682edd4f6f39f0b5706.1752826352.git.michal.simek@amd.com
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