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Change reg-shift property default to zero. When the integer property
is missing, it should be taken as zero. This is consistent to Linux
drivers/tty/serial/of_serial.c.
The x86 and most powerpc use reg-shift of 0. Most others use reg-shift
of 2. While reg-shift of 1 is rarely used.
Signed-off-by: Thomas Chou <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Signed-off-by: Vagrant Cascadian <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Signed-off-by: Vagrant Cascadian <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
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We now use the generic delay method which specifies the timeout as
microseconds instead of ticks.
Signed-off-by: Francois Retief <[email protected]>
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rk3036 mmc do not have internal dma, so we use fifo mode when read
and write data, we get the fifo mode and fifo depth property from
dts, pass to dw_mmc driver.
Signed-off-by: Lin Huang <[email protected]>
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register
emmc and sdcard have different register address, use non-removeable property
to distinguish them.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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some soc(rk3036 etc) use dw_mmc but do not have internal dma,
so we implement fifo mode to read and write data.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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the data transfer seem to long in the dwmci_send_cmd function,
so move this block as a separate funciton.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add a driver which support pin multiplexing setup for rk3036
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can
remove from SPL stage.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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This function looks up the controller and returns a pointer to each region
type.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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A PCI bus may be a bridge device where the controller is the bridge's
parent. Add a function to return the controller device, given a PCI device.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same type. The later ranges will overwrite the earlier
(configuration) ones.
There does not seem to be a way to distinguish the configuration ranges
other than by ordering (as per the device tree binding).
We could perhaps instead just store one region of each type in a simple
array. Once we are sure that we don't need to support multiple regions, we
could change this. It would be easier to do it when all drivers are
converted to use driver model for PCI.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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SDRAM doesn't always start at 0. Adjust the region mapping so that it works
on platforms where SDRAM is somewhere else.
This needs testing on other platforms.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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Move this option to Kconfig and fix up all users.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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To group all dm timer drivers together, move tsc timer to
drivers/timer directory.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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We should use device tree to pass the clock frequency of the timer
instead of hardcoded in the driver codes.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Since we have timer uclass to get clock frequency for us, remove
the custom version in the altera timer driver.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Thomas Chou <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Every timer device needs to have a valid clock frequency and it
can be specified in the device tree. Use pre_probe() to get this
in the timer uclass driver.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Thomas Chou <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This changes 'Timer' to 'timer' at several places.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Thomas Chou <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The PIO4 is introduced from SAMA5D2, as a new version
for Atmel PIO controller.
Signed-off-by: Wenyou Yang <[email protected]>
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The phy can share driver with other aquantia PHYs, so we only
add PHY ID.
Signed-off-by: Shaohui Xie <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: York Sun <[email protected]>
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BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.
Signed-off-by: York Sun <[email protected]>
Reported-by: Shengzhou Liu <[email protected]>
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Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <[email protected]>
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The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <[email protected]>
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LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <[email protected]>
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MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted
in several combinations of buffer size and frame offsets.
Workaround: Use buffers that are of size that is a multiple of 256, and
frame offset that is a multiple of 256"
Updating the DPNI Eth driver to comply with the restriction.
Signed-off-by: Bogdan Hamciuc <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add following debug information in the driver
- Get various DPNI counter values
- Get link status of DPNI objects
- Get information of both ends of connection (DPMAC - DPNI)
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.
Use DPMAC as net device where it represents physical lane.
Below modification done in driver
- Use global DPNI object
- Connect DPMAC to DPNI
- Create and destroy DPMAC
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.
Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.
Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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dpni_create API take takes more time as comapred to existing supported
APIs of MC Flib.
So increase MC command timeout.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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DPMAC represents physical line on the board. This physical
line eventually asscociate with on-board PHY.
So Add an api to return linked PHY ID of DPMAC object.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Current Management Complex Flibs does not support APIs for adding and
destroying the objects.
Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.
Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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