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In pch_gbe_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add pch_gbe_remove() to clean it up.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In designware_eth_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add designware_eth_remove() to clean it up.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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In phy_connect_dev(), if the phy device has an accociated mac device
before, a warning message will be printed. But we should test the
old device against the new one, if they are actually the same one,
don't print the warning message.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In get_phy_device_by_mask(), when no phy is found, currently we only
print a message to show the first phy address that is not found. But
this is not always the case as multiple phys can be specified by
phy_mask. Change to print all phys that are not found, and to reduce
the console boot log, change to use 'debug' instead of 'printf'.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In get_phy_device_by_mask(), when no phy is found, we should not
create any phy device.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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NAND-tree is used to check wiring between MAC and PHY using NAND gates
on the PHY side, hence the name.
NAND-tree initial status is latched at reset by probing the IRQ pin.
However some devices are sharing the PHY IRQ pin with other peripherals
such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000
display module, therefore they are switching the PHY in NAND-tree test
mode depending on the current IRQ line status at reset.
This patch ensure PHY is not in NAND-tree test mode only for the Micrel
KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I
doubt they are used on such weird hardware design.
Signed-off-by: Sylvain Rochet <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Casting from dev->priv to pci_dev_t changes the value's size on a 64-bit
system. This causes the compiler to complain about casting a pointer to an
integer of a different (smaller) size. To avoid this, cast to an integer
of matching size first, then perform an int->int cast to perform the size
change. This signals explicitly that we do want to change the size, and
avoids the compiler warning. This is legitimate since we know the pointer
actually stores a small integer, not a pointer value.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch adds support for Micrel KSZ8021RNL & KSZ8031RNL.
Signed-off-by: Sylvain Lemieux <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Using NAKs on empty RX fifo for bulk in transfers is the right choice
for a interrupt driven model, but U-Boot uses polling and expects an
immediate answer if there is no incoming packet. Using ZLP Bulk In Response
(BIR) mode avoids unexpected timeouts in the host controller driver.
As ZLP mode is reset default, there is no need to set it.
Signed-off-by: Stefan Brüns <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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codes related to phylib operations should be wrapped by CONFIG_PHYLIB.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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In convention, the '0' is a normal return value indicating there isn't
an error. While some functions of FMan IM driver treat '0' as an error
return value.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The FMan IM driver is developed for 32-bit platfroms and isn't
friendly to 64-bit platforms, so do the minimal refactor:
1. Refine the MURAM management and access.
2. Correct the initialization and operations for QDs and BDs.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The Frame Manager(FMan) is a big-endian peripheral, so the
registers, internal MURAM and BDs, which are allocated in main
memory and used to communication between core and FMan, should
be accessed in big-endian. The big-endian platforms can access
them directly as the code implemented so far, while for the
little-endian platforms it need to swap the byte-order.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Currently ldpaa ethernet driver rely on DPL file to statically configure
mac address for the DPNIs. It is not a correct approach.
Add support setting MAC address from env variable or Random MAC address.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal <[email protected]>
Reviewed-by: York Sun <[email protected]>
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smsc95xx_recv() does not reassemble bursts spread over multiple URBs.
If there is a lot of broadcast traffic, the fifo will fill up to the
burst cap limit. Lowering the burst cap to the URB size ensures no packet
spans multiple urbs.
Caveat, lower limit for working burst cap is 5/33 HS/FS packets.
Signed-off-by: Stefan Brüns <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Do not enable both I2C controllers by default. Enable them only when
they are selected.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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- Moved macro definitions to top
- Give tab space to CONFIG_ALTERA_SPI_IDLE_VAL value
- Re-arrange header includes ascending order
Acked-by: Thomas Chou <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in altera_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Marek Vasut <[email protected]>
Acked-by: Thomas Chou <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in xilinx_spi
Cc: Michal Simek <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in tegra*.c
Cc: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in omap3_spi
Cc: Nikita Kiryanov <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in fsl_qspi
Cc: York Sun <[email protected]>
Cc: Haikun Wang <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in designware_spi
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numeric mask hexcodes with GENMASK macro
in atmel_spi
Cc: Bo Shen <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in xilinx_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in ti_qspi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Vignesh R <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in tegra*.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in sh_qspi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Nobuhiro Iwamatsu <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in omap3_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Nikita Kiryanov <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in mpc8xxx_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in ich
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in fsl_*spi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: York Sun <[email protected]>
Cc: Haikun Wang <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in designware_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in cadence_qspi_apb
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Vikas Manocha <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in bfin_spi6xx
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Replace numerical bit shift with BIT macro
in atmel_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Bo Shen <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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GENMASK macro used on zynq_spi.c and zynq_qspi.c
GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)
Cc: Michal Simek <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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Used BIT macro on zynq_spi.c and zynq_qspi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Michal Simek <[email protected]>
Acked-by: Siva Durga Prasad Paladugu <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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This patch changes the cword union to use specific length types that are
architecture indepented.
This patch also renames the members of the cword union to represent
their usage, i.e.:
c -> w8
s -> w16
l -> w32
ll -> w64
Where "w" stands for "width" in bits.
I discovered this problem when enabling CFI flash on vexpress64.
cword.l was an unsigned long int, but it was intended to be 32 bits wide.
Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a
64-bit system fails when attempting to use 32-bit wide CFI flash parts.
Similar problems also existed with the other cword sizes.
Signed-off-by: Ryan Harkin <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The PEB array is an array of __be32, so let's fix the
scan_pool() prototype accordingly.
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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