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The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations.
Signed-off-by: Alexander Stein <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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This allows scanning the twl4030 keypad, storing the result in a 64-byte long
matrix with the twl4030_keypad_scan function.
Detecting a key at a given column and row is made easier with the
twl4030_keypad_key function.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This adds support for detecting a few inputs exported by the TWL4030.
Currently-supported inputs are the power button, USB and charger presence.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Paul Kocialkowski <[email protected]>
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This adds support for powering off (the omap3 SoC) from the twl4030. This is
especially useful when the kernel does not actually power off the device using
this method but reboots and leaves it up to the bootloader to actually turn the
power off.
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Przemyslaw Marczak <[email protected]>
Signed-off-by: Paul Kocialkowski <[email protected]>
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The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Acked-by: Scott Wood <[email protected]>
Tested-by: Sylvain Lemieux <[email protected]>
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Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.
NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Tom Warren <[email protected]>
Acked-by: Scott Wood <[email protected]>
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remove unneeded udelay() in this function, as we use
the dev_ready pin.
Signed-off-by: Heiko Schocher <[email protected]>
Acked-by: Scott Wood <[email protected]>
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The current 4.5 timeout for the autonegotiation are not enough to
complete it on my platform. Using the Intel E1000 PCIe card in the
Marvell db-mv784mp-gp eval board. So lets increase the timeout to
8 seconds.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Simon Glass <[email protected]>
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These were pointed out in review but I missed them.
Signed-off-by: Simon Glass <[email protected]>
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The return type of pmic_read and pmic_write is signed int, so
correct variable 'ret' from type unsigned int to int.
Signed-off-by: Peng Fan <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Przemyslaw Marczak <[email protected]>
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1. Add new regulator driver pfuze100.
* Introduce struct pfuze100_regulator_desc for maintaining info
for one regulator.
2. Add new Kconfig entry DM_REGULATOR_PFUZE100 for pfuze100.
3. This driver intends to support PF100, PF200 and PF3000.
4. Add related macro definition in pfuze header file.
Signed-off-by: Peng Fan <[email protected]>
Cc: Przemyslaw Marczak <[email protected]>
Cc: Simon Glass <[email protected]>
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1. Support driver model for pfuze100.
2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100
3. This driver intends to support PF100, PF200 and PF3000, so add
the device id into the udevice_id array.
4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS.
Signed-off-by: Peng Fan <[email protected]>
Cc: Przemyslaw Marczak <[email protected]>
Cc: Simon Glass <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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If there is no property named 'regulator-name' for regulators,
choose node name instead, but not directly return failure value.
Signed-off-by: Peng Fan <[email protected]>
Cc: Przemyslaw Marczak <[email protected]>
Cc: Simon Glass <[email protected]>
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The dw_mmc driver uses printf() in various places.
These bloat the code and cause problems for SPL. Use debug() where possible
and try to return a useful error code instead.
panto: Small rework to make it apply against top of tree.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Pantelis Antoniou <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
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Add Ethernet PHY for BCM Cygnus SoC
Signed-off-by: Jiandong Zheng <[email protected]>
Signed-off-by: Steve Rae <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.
Signed-off-by: Jörg Krause <[email protected]>
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phy_id is declared as u32 in create_phy_by_mask and in struct phy_device.
Signed-off-by: Jörg Krause <[email protected]>
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The rxbd is not correctly handled in case of a frame physical error
(FPE) or frame size error (FSE). The rxbd must be cleared and
advanced in case of an error to avoid receive stall.
Signed-off-by: Daniel Inderbitzin <[email protected]>
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LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.
It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.
Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Tested-by: Sylvain Lemieux <[email protected]>
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This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before this
change set bits related to PHY configuration in MAC2 and COMMAND
registers are rewritten by the following writing to the registers.
Without the change auto negotiation on boot quite often is not
completed in reasonable time:
Waiting for PHY auto negotiation to complete......... TIMEOUT !
Additionally MAC1_SOFT_RESET clear bit is removed since it is done in
preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead
added missing MCFG_RESET_MII_MGMT on device initialization.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
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The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX
MAC to some specified phy by phy id, by chance the single user of
lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may
have non-zero CONFIG_PHY_ADDR value, fix it.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Acked-by: Albert ARIBAUD (3ADEV) <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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According to LPC32x0 User Manual the following bits in Command
register 0x3106_0100 are defined:
Bit Symbol
2 - Unused
3 RegReset
4 TxReset
5 RxReset
Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets
an unused bit, but neglects RxReset.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Acked-by: Albert ARIBAUD (3ADEV) <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Tearing down an unitialized rx channel causes a pending address hole
event to be queued. When booting linux it will report this pending
as something like "Address Hole seen by USB_OTG at address 57fff584",
since u-boot did not handled this interrupt. Prevent that by not
tearing down the rx channel, when not receiving.
Signed-off-by: Jeroen Hofstee <[email protected]>
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Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.
Signed-off-by: Clemens Gruber <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Hao Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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- The EEE fixup magic should also be enabled for RGMII
- Improved comments
Signed-off-by: Clemens Gruber <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Hao Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch refer to linux kernel commit: d8b763e1e79f
net/macb: add TX multiqueue support for gem
by: Cyrille Pitchen
1. macb driver will check the register to find how many queues support for
this chip.
2. Then as we only use queue0 for tx, so we will set up all other queues
use a dummy descriptor, which USED bit is set. So those queues are not used.
Signed-off-by: Josh Wu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Initialize LCR rigister to configure
green LED for Link, yellow LED for Active.
Signed-off-by: Shengzhou Liu <[email protected]>
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remove unnecessary clearing of SWSM.SWSM_SMBI when obtaining the SW
semaphore. This was introduced in 951860634fdb557bbb58e0f99215391bc0c29779
while adding i210 support and should be now resolved by releasing the
semaphore when no longer needed.
Cc: Marcel Ziswiler <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Aneesh Bansal <[email protected]>
Cc: Naveen Burmi <[email protected]>
Cc: Po Liu <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Alison Wang <[email protected]>
Cc: Reinhard Arlt <[email protected]>
Cc: Shengzhou Liu <[email protected]>
Cc: York Sun <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
Tested-by: Bin Meng <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
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This reverts commit 17da7120249bfdef877f46be5bbcb3cc01212eb9.
The i210/i211 do have the SW_FW_SYNC (0x5b5c) register and this is what should
be used when acquiring the semaphore.
I believe the issue that this patch was trying to resolve is now resolved
by properly releasing the semaphore once no longer needed.
Cc: Marcel Ziswiler <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Aneesh Bansal <[email protected]>
Cc: Naveen Burmi <[email protected]>
Cc: Po Liu <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Alison Wang <[email protected]>
Cc: Reinhard Arlt <[email protected]>
Cc: Shengzhou Liu <[email protected]>
Cc: York Sun <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
Tested-by: Bin Meng <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
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Once the hwsw semaphore is acquired, it must be released when access to the
hw is completed. Without this subsequent calls to acquire will timeout
obtaining the semaphore.
Cc: Marcel Ziswiler <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Aneesh Bansal <[email protected]>
Cc: Naveen Burmi <[email protected]>
Cc: Po Liu <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Alison Wang <[email protected]>
Cc: Reinhard Arlt <[email protected]>
Cc: Shengzhou Liu <[email protected]>
Cc: York Sun <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
Tested-by: Bin Meng <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
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In case the data transfer failure happens, instead of returning
immediatelly, make sure the DMA is disabled, status register is
cleared and the bounce buffer is stopped.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Tom Rini <[email protected]>
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Endless timeouts are bad, since if we get stuck in one, we have no
way out. Zap this one by implementing proper timeout.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Tom Rini <[email protected]>
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The driver didn't stop the bounce buffer in case a data transfer
failed. This would lead to memory leakage if the communication
between the CPU and the card is unreliable. Add the missing call
to stop the bounce buffer.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Tom Rini <[email protected]>
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Currently the serial code assumes that there is always at least one serial
port (and panics / crashes due to null pointer dereferences when there is
none).
This makes it impossible to use u-boot on boards where there is no (debug)
serial port, because e.g. all uart pins are muxed to another function.
This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which
defaults to y (preserving existing behavior), which can be set to n on
such boards to make them work.
This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing
running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial,
and is not necessary at this moment.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add composite video out support.
This only gets enabled on the Mele M3 for now, since that is were it
was tested. It will be enabled on more boards after testing.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Add support for interlaced modes, this is a preparation patch for adding
composite out support.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Add a few extra sunxi display registers and constant defines.
Also rename some existing defines (e.g. dropping _GCTRL) and make
some more generic (e.g. dropping the 2x scaling from
SUNXI_LCDC_TCON1_TIMING_V_TOTAL).
This is a preparation patch for adding composite video out support.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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We should only subtract 2 from the vblank time when using tcon1.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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All the #ifdef-ery in selecting the default and fallback monitor type is
becoming unyielding and makes the code hard to read, replace it with a few
helper functions.
This will also be useful with the upcoming CHIP board which has display
adapter daughterboards which should be runtime detectable.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.
Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.
This patch removes the powering off calls, fixing the undesirable power
bouncing.
Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.
This commit also introduces the configurable options in Kconfig.
Signed-off-by: Peter Gielda <[email protected]>
Signed-off-by: Tomasz Gorochowik <[email protected]>
Signed-off-by: Mateusz Holenko <[email protected]>
Signed-off-by: Piotr Zierhoffer <[email protected]>
Signed-off-by: Karol Gugala <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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This driver adds NAND support to SPL.
It was tested on Allwinner A20.
Signed-off-by: Peter Gielda <[email protected]>
Signed-off-by: Tomasz Gorochowik <[email protected]>
Signed-off-by: Mateusz Holenko <[email protected]>
Signed-off-by: Piotr Zierhoffer <[email protected]>
Signed-off-by: Karol Gugala <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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Fix most of the dangling checkpatch issues, no functional change.
There are still 7 warnings, 1 checks , but those are left in place
for the sake of readability of the code.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Replace uintNN_t with uNN. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Actually convert the sequencer code to use socfpga_sdram_misc_config
instead of the various macros. This is just an sed exercise here, no
manual coding needed.
This patch actually removes the need to include any board-specific
files in sequencer.c , so sequencer.c namespace is now no longer
poluted by QTS-generated macros.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
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