| Age | Commit message (Collapse) | Author |
|---|
|
Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Make it easier for the user to notice when the MC firmware
had problems booting.
Signed-off-by: J. German Rivera <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <[email protected]>
|
|
In case SPD address changes between board revisions, updating SPD
address can be called from board file.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
|
|
Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug("addr=%08lx, size=%08lx\n",
^
Signed-off-by: Haikun Wang <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
|
|
|
|
We should not leave the expansion ROM address window open when there
is not a valid ROM.
Suggested-by: Matt Porter <[email protected]>
Signed-off-by: Bin Meng <[email protected]>
Tested-by: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Andrew Bradford <[email protected]>
|
|
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Jian Luo <[email protected]>
|
|
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.
Signed-off-by: Jian Luo <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Bin Meng <[email protected]>
|
|
Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.
Signed-off-by: Simon Glass <[email protected]>
|
|
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model is
enabled for PCI.
Also add a comment to explain the problem.
Signed-off-by: Simon Glass <[email protected]>
|
|
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.
Signed-off-by: Bin Meng <[email protected]>
|
|
Include <errno.h> otherwise ENOSYS is undefined.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Tidy up three minor problems in this file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
|
|
|
|
|
|
Since commit 09c3280754f8 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.
=> nand read 80000000 10000 10000
NAND read: Offset exceeds device limit
=> nand erase 100000 100000
NAND erase: Offset exceeds device limit
The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.
Acked-by: Heiko Schocher <[email protected]>
Acked-by: Scott Wood <[email protected]>
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.
Tested on DB-88F6280-GP eval board.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Cc: Luka Perkov <[email protected]>
|
|
This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.
This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Hans de Goede <[email protected]>
Cc: Luka Perkov <[email protected]>
|
|
While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.
This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.
Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Luka Perkov <[email protected]>
|
|
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Luka Perkov <[email protected]>
|
|
When driver model is not used the current code does not correctly select
the pinmux for the I2C bus. This bug was introduced by this commit:
8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Reviewed-by: Przemyslaw Marczak <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
The temperature calculation must be typecasted to keep the compiler
from sign extending a negative value prior to division.
This fixes an issue where if the CPU temperature is <0C it will get stuck
in the busywait loop until the CPU heats up to 0C.
Cc: Ye Li <[email protected]>
Cc: Jason Liu <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
|
|
Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four
I2C instances available in VF610.
Signed-off-by: Albert ARIBAUD (3ADEV) <[email protected]>
|
|
This locally defined struct is actually only used once
and as an opaque type. Remove it for clarity.
Signed-off-by: Albert ARIBAUD (3ADEV) <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
|
|
Remove the check for temperature being within the min/max range and enter the
busywait cooling loop whenever the CPU temperature is over the critical temp.
This fixes the issue where if a board was booted at a temp greater than
the CPU temperature max, it would skip the loop and never indicate or try
to address the overtemp issue.
Cc: Ye Li <[email protected]>
Cc: Jason Liu <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
|
|
When compling under 64bit platforms, there are lots of warnings,
like:
drivers/block/ahci.c:114:18: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
......
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Tang Yuantian <[email protected]>
|
|
commit f566c99 "net: Update hardware MAC address if it changes in env"
removes writing MAC address to designware controller after soft reset.
This makes designware ethernet port fail to work. Actually the MAC
address should always be programmed after soft reset.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
|
|
|
|
Added UART DCC support for armv8
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
|
|
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
Signed-off-by: Axel Lin <[email protected]>
Tested-by: Albert ARIBAUD <[email protected]>
|
|
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha <[email protected]>
Tested-by: Stefan Roese <[email protected]>
Reviewed-by: Jagannadh Teki <[email protected]>
|
|
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha <[email protected]>
Tested-by: Stefan Roese <[email protected]>
Reviewed-by: Jagannadh Teki <[email protected]>
|
|
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.
Signed-off-by: Vikas Manocha <[email protected]>
Tested-by: Stefan Roese <[email protected]>
Reviewed-by: Jagannadh Teki <[email protected]>
|
|
Fix compilation warnings for redefined 'clamp' macro and non-uniform
clamp macro types.
Signed-off-by: Angelo Dureghello <[email protected]>
Reviewed-by: Jagannadh Teki <[email protected]>
|
|
Added SPI_FLASH_BAR entry on Kconfig with help description
Signed-off-by: Jagan Teki <[email protected]>
|
