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IFC controller v1.1.0 requires internal SRAM initialize by reading
NAND flash. Higher controller versions have provided "SRAM init" bit in
NCFGR register space.
update SRAM initialize logic to reflect the same.
Also print error message in case of Page read error.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.
Update MAX_BANKS same as SoC defined
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.
Signed-off-by: Zhao Qiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Some of the fm_port_to_index() callers did not check for -1 return value and
used -1 as an array index.
Signed-off-by: Marian Rotariu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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In 73545f75b66d "ahci: wait longer for link" I increased the
timeout to 40ms based on the observed behaviour of a WD disk on a
Cubietruck. Since then Karsten Merker and myself have both
observed timeouts with HGST disks (Karsten on Cubietruck, me on
Cubieboard2). Increasing the timeout to ~175ms fixes this, so go
to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell <[email protected]>
Cc: Karsten Merker <[email protected]>
Acked-by: Hans de Goede <[email protected]>
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Just for type checking.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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The function still returns the same value.
The comment block is no longer necessary because our intention is
clear enough by using DIV_ROUND_CLOSEST() macro.
Signed-off-by: Masahiro Yamada <[email protected]>
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If CONFIG_OMAP1610 is defined, the code returning the fixed value (26)
is enabled. But this case is covered by the following code.
(CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
(MODE_X_DIV * gd->baudrate)
= (48000000 + (115200 * (16 / 2))) / (16 * 115200)
= 48921600 / 1843200
= 26
The "#ifdef CONFIG_OMAP1610" was added by commit 6f21347d more than
ten years ago. In those days, the divide-and-round was not used.
I guess that is why this weird code was added here.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Rishi Bhattacharya <[email protected]>
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upper_32_bits() and lower_32_bits() have been ported into linux/compat.h.
Start use them now in drivers/usb/host/xhci.h.
Signed-off-by: Lijun Pan <[email protected]>
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Add missing prototypes for global functions and
make local functions static.
cc: [email protected]
Signed-off-by: Jeroen Hofstee <[email protected]>
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use weak instead of alias to prevent some clang warnings.
Signed-off-by: Jeroen Hofstee <[email protected]>
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lists.c / root.c do not include their own header and they
could potentially implement a different function. Therefore
actually include the headers.
cc: [email protected]
Signed-off-by: Jeroen Hofstee <[email protected]>
Acked-by: Simon Glass <[email protected]>
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clang warns this check is silly; it is since s is
a local variable.
u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of
array 's' not equal to a null pointer is always true
else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
cc: Stefan Roese <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
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This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Ma Haijun <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Cc: Henrik Nordström <[email protected]>
Cc: Tom Cubie <[email protected]>
Acked-by: Hans de Goede <[email protected]>
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Add support for the x-powers axp152 pmic which is found on most A10s boards
and enable it for the r7-tv-dongle board.
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Ian Campbell <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Add support for the x-powers axp209 pmic which is found on most A10, A13 and
A20 boards.
And enable AXP209 support for the Cubietruck and Cubieboard boards.
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
Acked-By: Prafulla Wadaskar <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
[ ijc -- updated u-boot-spl-fel.lds ]
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Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).
The kirkwood changes have been compile tested using the wireless_space board
config, the orion5x changes have been compile tested using the edminiv2 board
config.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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Add support for 3rd and 4th I2C.
Signed-off-by: Shengzhou Liu <[email protected]>
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If a bus busy is detected when intializing the driver,
toggle 9 times the scl pin. Therefore enable the test mode
of the controller, in which the scl, sda pins can be
controlled manually.
Tested on the siemens boards pxm2, rut and dxr2.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Hannes Petermaier <[email protected]>
Cc: Lubomir Popov <[email protected]>
Cc: Steve Sakoman <[email protected]>
Cc: Sandeep Paulraj <[email protected]>
Cc: Vincent Stehlé <[email protected]>
Cc: Samuel Egli <[email protected]>
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Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.
Signed-off-by: Felipe Balbi <[email protected]>
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some boards won't work if the PHY isn't explicitly
powered up.
Signed-off-by: Felipe Balbi <[email protected]>
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Signed-off-by: Dirk Eibach <[email protected]>
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IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibach <[email protected]>
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get_sclk() was not defined in bfin_wdt.c, include the corresponding header.
Cc: Sonic Zhang <[email protected]>
Signed-off-by: Vasili Galka <[email protected]>
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This board is old enough and has no maintainer.
Signed-off-by: Masahiro Yamada <[email protected]>
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This board is old enough and has no maintainer.
Signed-off-by: Masahiro Yamada <[email protected]>
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada <[email protected]>
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clang is tempted to inteprete such a condition as a assignment
as well. Since it isn't don't use double brackets.
cc: Tom Wai-Hong Tam <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
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The directory arch/${ARCH}/cpu/${CPU} does not exist
in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86.
These architectures have only one CPU type.
Defining CPU should not be required for such architectures.
This commit allows cpu field (= the 3rd field of boards.cfg)
to be kept blank.
Signed-off-by: Masahiro Yamada <[email protected]>
Cc: Andreas Bießmann <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Thomas Chou <[email protected]>
Cc: Stefan Kristiansson <[email protected]>
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There have been 3 versions of the sunxi_emac support patch during its
development. Somehow version 2 ended up in upstream u-boot where as
the u-boot-sunxi git repo got version 3.
This bumps the version in upstream u-boot to version 3 of the patch:
- Initialize MII clock earlier so mii access to allow independent use
- Name change from WEMAC to EMAC to match mainline kernel & chip manual
- Cosmetic code cleanup
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Henrik Nordstrom <[email protected]>
Signed-off-by: Oliver Schinagl <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the
dma descriptors on the stack, and then exits while the dma transfer is in
progress, so the dma engine is reading stack memory which at that point may
be re-used. So far we've gotten away with this by luck, but recent u-boot
changes have shifted the stack start address by 16 bytes, which combined
with dma alignment now exposes this problem.
Since we end up just busy waiting for the dma engine anyway, this commit
fixes things by simply removing the dma code, resulting in smaller bug-free
code.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
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This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev <[email protected]>
Cc: [email protected]
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In current gpio_set_value() implementation, it always sets the gpio control bit
no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
This patch fixes this bug.
The address bus is used as a mask on read/write operations, so that independent
software drivers can set their GPIO bits without affecting any other pins in a
single write operation. Thus we don't need a read-modify-write to update the
register.
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Reviewed-by: Vipin Kumar <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
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Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.
Signed-off-by: J. German Rivera <[email protected]>
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Lijun Pan <[email protected]>
Signed-off-by: Shruti Kanetkar <[email protected]>
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Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Varun Sethi <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
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Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump
the address length (alen) too, so the address value can be correctly
interpreted.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
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The Tegra I2C controller's TX FIFO contains 32-bit words. If the final
FIFO entry of a transaction contains fewer than 4 bytes, the driver
currently fills the unused FIFO bytes with uninitialized data. This can
be confusing when reading back the FIFO content for debugging purposes.
Solve this by explicitly initializing the variable containing FIFO data
before filling it (partially) with data. With this change,
send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e.
read) branch.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
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I2C read transactions are typically implemented as follows:
START(write) address REPEATED_START(read) data... STOP
However, Tegra's I2C driver currently implements reads as follows:
START(write) address STOP START(read) data... STOP
This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
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Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and
"ci_ep" for a struct ci_ep. This is nice and consistent, and helps people
know what type a variable is without searching for the declaration.
handle_ep_complete() doesn't do this, so fix it to be consistent.
Signed-off-by: Stephen Warren <[email protected]>
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A UDC's alloc_request method should zero out the newly allocated request.
Ensure the Atmel driver does so. This issue was found by code inspection,
following the investigation of an intermittent issue with ci_udc, which
was tracked down to failing to zero out allocated requests following some
of my changes. All other UDC drivers already zero out requests in one
way or another.
Signed-off-by: Stephen Warren <[email protected]>
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struct ci_req is a purely software structure, and needs no specific
memory alignment. Hence, allocate it with calloc() rather than
memalign(). The use of memalign() was left-over from when struct ci_req
was going to hold the aligned bounce buffer, but this is now dynamically
allocated.
Signed-off-by: Stephen Warren <[email protected]>
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There's no need to store an array of QTD pointers in the controller.
Since the calculation is so simple, just have ci_get_qtd() perform it
at run-time, rather than pre-calculating everything.
Signed-off-by: Stephen Warren <[email protected]>
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2 QTDs are allocated for each EP. The current allocation scheme aligns
the first QTD in each pair, but simply adds the struct size to calculate
the second QTD's address. This will result in a non-cache-aligned
addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the
size of struct ept_queue_item).
Similarly, the original ilist_ent_sz calculation aligned the value to
ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment
requirement into account. This doesn't cause a practical issue unless
ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may
as well fix the code to be explicit, so it's obviously completely
correct.
The new value of ILIST_ENT_SZ takes all alignment requirements into
account, so we can simplify ci_{flush,invalidate}_qtd() by simply using
that macro rather than calling roundup().
Similarly, the calculation of controller.items[i] can be simplified,
since each QTD is evenly spaced at its individual alignment requirement,
rather than each pair being aligned, and entries within the pair being
spaced apart only by structure size.
Signed-off-by: Stephen Warren <[email protected]>
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This will allow functions other than ci_udc_probe() to make use of the
constants in a future change.
This in turn requires converting the const int variables to #defines,
since the initialization of one global const int can't depend on the
value of another const int; the compiler thinks it's non-constant if
that dependency exists.
Signed-off-by: Stephen Warren <[email protected]>
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Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly
call ci_get_qtd() to find the address of the other QTD to use. This
will allow us to correctly align each QTD individually in the future,
which may involve leaving a gap between the QTDs.
Signed-off-by: Stephen Warren <[email protected]>
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