| Age | Commit message (Collapse) | Author |
|---|
|
This patch removed obscure restriction on the HW setting of DMA transfers.
Before this change each transaction sent up to 512 bytes (with packet count
equal to 1) for non EP0 transfer.
Now it is possible to setup DMA transaction up to DMA_BUFFER_SIZE.
Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`
Measurement:
Transmission speed: 20.74 MiB/s
Signed-off-by: Lukasz Majewski <[email protected]>
Cc: Marek Vasut <[email protected]>
|
|
A set of cache operations (both invalidation and flush) were redundant
in the S3C HS OTG Samsung driver:
1. s3c_udc_ep0_zlp - to transmit EP0's ZLP packets one don't need to flush
the cache (since it is the zero length transmission)
2. s3c_udc_pre_setup and s3c_ep0_complete_out - cache invalidation is not
needed when the buffer for OUT EP0 transmission is setup, since no data
has yet arrived.
Cache cleanups presented above don't contribute much to transmission speed
up, hence shall be regarded as cosmetic changes.
3. setdma_rx - here the s3c UDC driver's internal buffers were invalidated.
This call is not needed anymore since we reuse the buffers passed from
gadgets. This is a key contribution to transmission speed improvement.
Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`
Measurements:
Base values (without improvement):
Transmission speed: 9.51 MiB/s
After the change:
Transmission speed: 10.15 MiB/s
Signed-off-by: Lukasz Majewski <[email protected]>
Cc: Marek Vasut <[email protected]>
|
|
Calls to malloc() have been replaced by memalign. It now provides proper
buffer alignment.
Signed-off-by: Lukasz Majewski <[email protected]>
Cc: Marek Vasut <[email protected]>
|
|
This patch fix the u-boot shell problem on TRATS2 board.
- If hold the key while booting is in progress,
white spaces are written in u-boot shell.
Set Automatically clears after resetting Rx FIFO.
Signed-off-by: Inha Song <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Acked-by: Lukasz Majewski <[email protected]>
Tested-by: Lukasz Majewski <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
|
|
|
|
Just to be sure that there is no pending data.
Signed-off-by: Michal Simek <[email protected]>
|
|
As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.
Signed-off-by: Michal Simek <[email protected]>
|
|
Tegra124's MMC controller is very similar to earlier SoC generations,
and can be supported by the same driver.
However, there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW. This
patch updates the driver to support that new compatible value.
That said, the HW differences are only relevant when enabling certain
high-performance transfer modes. Since the driver is currently very
simple and doesn't enable those modes, we don't actually need to address
any of these HW differences in the code yet, hence the simple nature of
this patch.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So update acessor functions with common IFC acessor functions to take care
both type of endianness.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Acked-by: York Sun <[email protected]>
|
|
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
Define MDIO related configs
Added eth.c file
Update t1040.c to support RGMII and SGMII
Update t1040qds.c to support ethernet
Define the PHY address
Signed-off-by: Arpit Goel <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <[email protected]>
|
|
Current print only display width of PCIe device. Add print to display
PCIe generation supported by the device.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Now fimd BPP color mode depends on vl_bpp value in struct "panel_info".
There is only 16BPP mode check, default mode is 24BPP.
Other fimd modes are usually unneeded and also needs some fimd driver
modifications and tests.
Signed-off-by: Przemyslaw Marczak <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Changes:
new file:
- board/samsung/common/misc.c
depends on: CONFIG_MISC_COMMON
- move draw_logo() to misc.c
configs: trats, trats2, universal:
- enable CONFIG_MISC_COMMON,
- enable CONFIG_MISC_INIT_R,
- add misc_init_r() and call draw_logo() in it.
Signed-off-by: Przemyslaw Marczak <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Remove wrong and unused env variables
Trats2 is not as GT-I8800.
Signed-off-by: Przemyslaw Marczak <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Cc: Piotr Wilczek <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Old s5p gpio coding method was not clean and was not working properly
for all parts and banks. New method is clean and easy to extend.
Gpio coding mask:
0x000000ff - pin number
0x00ffff00 - bank offset
0xff000000 - part number
Signed-off-by: Przemyslaw Marczak <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
|
|
Signed-off-by: Masahiro Yamada <[email protected]>
|
|
The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Card detection pin is ineffective on T4240QDS Rev1.0.
There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so
For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.
This workaround force sdhc driver scan and initialize the card
regardless of whether the card is inserted or not in case Rev1.0.
Signed-off-by: Haijun Zhang <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'.
When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before.
Signed-off-by: Shengzhou Liu <[email protected]>
Acked-by: York Sun <[email protected]>
|
|
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two debug registers changed by the workaround.
Signed-off-by: York Sun <[email protected]>
CC: Ben Collins <[email protected]>
CC: James Yang <[email protected]>
|
|
- add more serdes protocols support.
- fix some serdes lanes route.
- fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d.
- correct boot location info for SD/SPI boot.
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
|
|
As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.
Signed-off-by: Michal Simek <[email protected]>
|
|
|
|
The omap_gpmc allows switching ecc at runtime. Since
the NAND_SUBPAGE_READ flag is only set, it is kept when
switching to hw ecc, which is not correct. This leads to
calling chip->ecc.read_subpage which is not a valid
pointer. Therefore clear the flag when switching ecc so
reading in hw mode works again.
Cc: Scott Wood <[email protected]>
Cc: Pekon Gupta <[email protected]>
Cc: Nikita Kiryanov <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
|
|
|
|
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
|
|
Use the same masks as used in the kernel:
https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6
With such changes Ethernet is functional on hummingboard solo.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Patch: 306640
|
|
Don't know why but, file permission was changed
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Issues:
- reading i2c data by passing u16 pointer causes errors in read data.
- max17042 status register fields have not only Power On Reset meaning
so using proper mask is required.
Changes:
- read i2c data to type u32 instead of u16 - avoids buffer overflow
- compare FG status register using mask not just one bit value
- add checking return value to functions fg read/write
- add model lock and model check count
- add debug msg
Signed-off-by: Przemyslaw Marczak <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Minkyu Kang <[email protected]>
|
|
|
|
|
|
Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo
controller, connected to HSIC Phy of USB host controller via USB3503 hub.
This patch uses board specific board_usb_init function to perform reset
sequence for USB3503 hub and enables the relevant config options for
network to work.
Signed-off-by: Inderpal Singh <[email protected]>
Signed-off-by: Chander Kashyap <[email protected]>
|
|
The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2
are for HSIC phys. The usb 2.0 phy is already being setup. This patch
sets up the hsic phys.
Signed-off-by: Inderpal Singh <[email protected]>
|
|
The fifo size of ep0 is 64 bytes, and if the packet size grater than
64 bytes, the driver would have to fill up the fifo multiple times,
and before filling up the fifo, the driver should make sure the fifo
is empty by checking fifo empty indication.
However there is a hardware bug that the fifo empty indication is
somehow a bit earlier than fifo reset. So if I don't add an extra
delay here, the data might be corrupted. (i.e., 1 byte missing)
After a couple of tests, it truns out that 1 usec is good enough.
This workaround should be applied to all hardware revisions.
Signed-off-by: Kuo-Jung Su <[email protected]>
CC: Marek Vasut <[email protected]>
|
|
Since hardware revision 1.11.0, the following interrupt status
registers are now W1C (i.e., write 1 clear):
1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5)
2. Interrupt Source Group 2 Register (0x14C) (All bits)
And before revision 1.11.0, these registers are all R/W.
Which means software must write a 0 to clear the status.
Signed-off-by: Kuo-Jung Su <[email protected]>
CC: Marek Vasut <[email protected]>
|
|
This fixes the following compiler warnings:
fti2c010.c: In function 'fti2c010_read':
fti2c010.c:204:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized]
fti2c010.c: In function 'fti2c010_write':
fti2c010.c:266:8: warning: 'paddr' may be used uninitialized in this function [-Wuninitialized]
Signed-off-by: Kuo-Jung Su <[email protected]>
Cc: Heiko Schocher <[email protected]>
|
|
Since we agreed on legacy implementation of "eeprom_{read|write}"
(http://patchwork.ozlabs.org/patch/295825/) I had to fix/make it work
again DesignWare I2C driver for cases when 1 EEPROM IC fake I2C with
anumber of "built-in" ICs with different chip addresses.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Tom Rini <[email protected]>
cc: Armando Visconti <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Vipin KUMAR <[email protected]>
Cc: Tom Rix <[email protected]>
Cc: Mischa Jonker <[email protected]>
Cc: Kuo-Jung Su <[email protected]>
|
|
This corrects i2c core to interpret the value returned by
i2c_set_bus_speed as a success indicator rather than the
actual speed that was set. When i2c_set_bus_speed returns
a failure code, the speed is unknown so the adapter speed
is set to zero.
Signed-off-by: Darwin Rambo <[email protected]>
Reviewed-by: Tim Kryger <[email protected]>
Reviewed-by: Steve Rae <[email protected]>
Acked-by: Jagannadha Sutradharudu Teki <[email protected]>
|
|
Signed-off-by: Hisashi Nakamura <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Signed-off-by: Hisashi Nakamura <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
The array reserved as a placeholder in the structure ipu_idmac
should contain 44 32bit unsigned integer entries instead of 45
ones, because the placeholder is located bewteen the register
IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address
offsets of 0x804c and 0x8100 respectively.
Reported-by: Robin Gong <[email protected]>
Acked-by: Robin Gong <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
|
|
The array reserved1 as a placeholder in the structure ipu_cm
should contain 4 32bit unsigned integer entries instead of 16
ones, because the placeholder is located bewteen the register
IPU_CH_DB_MODE_SEL_1 and the register IPU_ALT_CH_DB_MODE_SEL_0
with the address offsets of 0x154 and 0x168 respectively.
Reported-by: Robin Gong <[email protected]>
Acked-by: Robin Gong <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
|
|
Remove the flag SECT_4K for device N25Q128 as the 4K-byte
sub sector erase granularity is available only for top/bottom
8 sectors in some of the N25Q128 chips.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
|
|
This config will use for defining greater than single flash support.
currently - DUAL_STACKED and DUAL_PARALLEL.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
|
|
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
|
|
This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
|
