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As per OMAP3530 TRM referenced below [1]
For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
- OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
- OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device
Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
*for x8 NAND Device*
+--------+---------+---------+---------+---------+---------+---------+
| xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
+--------+---------+---------+---------+---------+---------+---------+
*for x16 NAND Device*
+--------+--------+---------+---------+---------+---------+---------+---------+
| xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
+--------+--------+---------+---------+---------+---------+---------+---------+
This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.
[1] OMAP3530: http://www.ti.com/product/omap3530
TRM: http://www.ti.com/litv/pdf/spruf98x
Chapter-25: Initialization Sub-topic: Memory Booting
Section: 25.4.7.4 NAND
Figure 25-19. ECC Locations in NAND Spare Areas
Reported-by: Stefan Roese <[email protected]>
Signed-off-by: Pekon Gupta <[email protected]>
Tested-by: Stefan Roese <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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Before switching to the real Kbuild, drivers/usb/gadget/Makefile
must be fixed.
If none of CONFIG_USB_GADGET, CONFIG_USB_ETHER, CONFIG_USB_DEVICE
is defined, both obj- and obj-y get empty.
We need non-empty obj- or obj-y on each Makefile
to generate built-in.o on the real Kbuild.
Signed-off-by: Masahiro Yamada <[email protected]>
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For LPC32XX high-speed UART it is required to send a carriage return
symbol along with line feed. The problem was introduced in e503f90a
commit.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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As mEMAC1 and mEMAC2 are dual-role MACs, which are used as 1G or 10G MAC.
So we update dynamically 'cell-index' to '2' and '3' for 10GEC3 and 10GEC4.
Also change 'fsl,fman-port-1g-rx' to 'fsl,fman-port-10g-rx', ditto for Tx.
Signed-off-by: Shengzhou Liu <[email protected]>
Acked-by: York Sun <[email protected]>
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Conflicts:
board/samsung/trats2/trats2.c
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <[email protected]>
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Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard
Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compulab/cm_t335/u-boot.lds
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Signed-off-by: Soren Brinkmann <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write. Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.
[email protected] added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This adds a SPI framework for people to hook up simulated SPI clients.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.
Signed-off-by: Simon Glass <[email protected]>
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Signed-off-by: Andreas Bießmann <[email protected]>
Acked-by: Jens Scharsig (BuS Elektronik)<[email protected]>
Tested-by: Jens Scharsig (BuS Elektronik)<[email protected]>
Acked-by: Scott Wood <[email protected]>
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This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.
Signed-off-by: Andreas Bießmann <[email protected]>
Tested-by: Bo Shen <[email protected]>
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Faraday FTSDC021 is a controller which is compliant with
SDHCI v3.0, SDIO v2.0 and MMC v4.3.
However this driver is only verified with SD memory cards.
Signed-off-by: Kuo-Jung Su <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
CC: Andy Fleming <[email protected]>
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Existing eSDHC SPL framework assumes booting from sd-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
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If platform provides "host->fifoth_val" it will be used for
initialization of DWMCI_FIFOTH register. Otherwise default value will be
used.
This implementation allows:
* escape unclear and recursive calculations that are currently in use
* use whatever custom value for DWMCI_FIFOTH initialization if any
particular SoC requires it
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Mischa Jonker <[email protected]>
Cc: Alim Akhtar <[email protected]>
Cc: Rajeshwari Shinde <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Amar <[email protected]>
Cc: Kyungmin Park <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Andy Fleming <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
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dw-mmc.c is the general driver file.
So, remove the exynos specific code at dw-mmc.c.
Instead, exynos specific cod can be move into exynos-dw_mmc.c.
Signed-off-by: Jaehoon Chung <[email protected]>
Acked-by: Alexey Brodkin <[email protected]>
Acked-by: Pantelis Antoniou <[email protected]>
Acked-by: Minkyu Kang <[email protected]>
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In commit bb1f327 we removed the UHH reset to fix NFS root (over usb
ethernet) problems with Beagleboard (3530 ES1.0). However, this
seems to cause USB detection problems for Pandaboard, about (3/8).
On further investigation, it seems that doing the UHH reset is not
the cause of the original Beagleboard problem, but in the way the reset
was done.
This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based
on the UHH_REVISION register. This should fix the Beagleboard NFS
problem as well as the Pandaboard USB detection problem.
Reported-by: Tomi Valkeinen <[email protected]>
CC: Stefan Roese <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
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For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Scott Jiang <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Scott Jiang <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels
on Exynos5420 and Exynos5250 and also adds support for init function
for hsi2c channels
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
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Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
based devices. This seems to be related to the following advisory which
apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
OMAP4430 TRM:
Advisory:
I2C Module Does Not Allow 0-Byte Data Requests
Details:
When configured as the master, the I2C module does not allow 0-byte data
transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause
undefined behavior.
Workaround(s):
No workaround. Do not use 0-byte data requests.
The writes in question are unnecessary from a functional point of view.
Most of them are done after I/O has finished, and the only one that preceds
I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before
actual data transmission takes place.
Therefore, remove all writes that zero the cnt register.
Cc: Heiko Schocher <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Lubomir Popov <[email protected]>
Cc: Enric Balletbo Serra <[email protected]>
Signed-off-by: Nikita Kiryanov <[email protected]>
Tested-by: Thomas Petazzoni <[email protected]>
Tested-by: Lubomir Popov <[email protected]>
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For a eeprom with a 2-bytes address (e.g., Ateml AT24C1024B),
the r/w address should be serial out in MSB order.
Signed-off-by: Kuo-Jung Su <[email protected]>
Cc: Heiko Schocher <[email protected]>
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Replace the legacy i2c model with the new one.
Signed-off-by: Kuo-Jung Su <[email protected]>
Cc: Heiko Schocher <[email protected]>
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Coding style cleanup
Signed-off-by: Kuo-Jung Su <[email protected]>
Cc: Heiko Schocher <[email protected]>
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Fix clock value initialisation for Exynos other than Exynos5 for hsi2c.
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Cc: Minkyu Kang <[email protected]>
Cc: Heiko Schocher <[email protected]>
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This patch adapts the s3c24x0 driver to the new i2c framework.
Config file is modified for all the boards that use the driver.
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
CC: Minkyu Kang <[email protected]>
CC: Heiko Schocher <[email protected]>
CC: Inderpal Singh <[email protected]>
CC: David Müller <[email protected]>
CC: Chander Kashyap <[email protected]>
CC: Lukasz Majewski <[email protected]>
Tested-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Naveen Krishna Chatradhi <[email protected]>
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Existing eSPI SPL framework assumes booting from spi-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain <[email protected]>
Acked-by: York Sun <[email protected]>
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In 48ec5291, only TX path was optimized; this does the same also for RX
path. This results in huge increase of TFTP throughput on custom am3352
board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer
timeouts.
Signed-off-by: Vladimir Koutny <[email protected]>
Cc: Mugunthan V N <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Tom Rini <[email protected]>
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Align the ATA ID buffer to the cache-line boundary. This gets rid
of the below error mesages on ARM v7 platforms.
scanning bus for devices...
ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818
CC: Aneesh V <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
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If malloc() fails, we don't want to continue in ahci_init() and
ahci_init_one(). Also print a more informative error message on
malloc() failures.
CC: Rob Herring <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
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Added chip type detection and twl6032
support in the battery control
and charge functions.
Based on Balaji T K <[email protected]> patches for TI u-boot.
Signed-off-by: Oleg Kosheliev <[email protected]>
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The data struct is used to support different
PMIC chip types. It contains the chip type and
the data (e.g. registers addresses, adc multiplier)
which is different for twl6030 and twl6032.
Replaced some hardcoded values with the
structure vars.
Based on Balaji T K <[email protected]> patches for TI u-boot.
Signed-off-by: Oleg Kosheliev <[email protected]>
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We should return a negative error number (-EINVAL) on error.
Signed-off-by: Fabio Estevam <[email protected]>
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Signed-off-by: Soren Brinkmann <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Series-to: trini, uboot
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This patch add new defines for usb phy for Exynos4x12.
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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There is no need to pass p->bus differently when the PMIC is connected via SPI
or via I2C.
Handle the both cases in the same way.
Signed-off-by: Fabio Estevam <[email protected]>
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Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <[email protected]>
Acked-by: York Sun <[email protected]>
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There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.
Signed-off-by: Shengzhou Liu <[email protected]>
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Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.
Signed-off-by: York Sun <[email protected]>
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The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun <[email protected]>
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Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.
Signed-off-by: York Sun <[email protected]>
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