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This patch adds the driver for keyboard that's controlled by ChromeOS EC.
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Vincent Palatin <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This patch adds LPC support for carrying out the cros_ec protocol.
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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This patch adds SPI support for carrying out the cros_ec protocol.
Signed-off-by: Hung-ying Tyan <[email protected]>
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This patch adds I2C support for carrying out the cros_ec protocol.
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.
Signed-off-by: Bernie Thompson <[email protected]>
Signed-off-by: Bill Richardson <[email protected]>
Signed-off-by: Che-Liang Chiou <[email protected]>
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Hung-ying Tyan <[email protected]>
Signed-off-by: Louis Yung-Chieh Lo <[email protected]>
Signed-off-by: Randall Spangler <[email protected]>
Signed-off-by: Sean Paul <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Vincent Palatin <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Call s5p_gpio_set_value() to avoid code duplication.
Signed-off-by: Axel Lin <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Current code had writel arguments the wrong way around, fix it.
Signed-off-by: Axel Lin <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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add atheros ar803x phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Joe Hershberger <[email protected]>
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add natsemi dp83630 phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Signed-off-by: Kuo-Jung Su <[email protected]>
CC: Joe Hershberger <[email protected]>
CC: Tom Rini <[email protected]>
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Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: Invalid!!!
Signed-off-by: Kuo-Jung Su <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Tom Rini <[email protected]>
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Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read
Signed-off-by: Leo Sartre <[email protected]>
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Add gigabit MAC support in macb driver
- using IP version to distinguish whether MAC is GMAC
Signed-off-by: Bo Shen <[email protected]>
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using phylib to configure phy device in macb driver
Signed-off-by: Bo Shen <[email protected]>
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Using CONFIG_AT91FAMILY replace #ifdeferry for atmel SoC
Signed-off-by: Bo Shen <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
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The device interface is 16 bits wide.
All the available packets are read from the incoming fifo.
Signed-off-by: Roberto Cerati <[email protected]>
Signed-off-by: Raffaele Recalcati <[email protected]>
[[email protected]: address comments from review results]
[[email protected]: clean up for submit]
Signed-off-by: Bo Shen <[email protected]>
Tested-by: Raffaele Recalcati <[email protected]>
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Signed-off-by: Xie Xiaobo <[email protected]>
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commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell <[email protected]>
Date: Tue Feb 19 08:27:33 2013 -0500
Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)
Signed-off-by: Charles Coldwell <[email protected]>
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Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid
code duplication
Signed-off-by: David Andrey <[email protected]>
Cc: Troy Kisky <[email protected]>
Cc: Joe Herschberger <[email protected]>
Cc: Andy Fleming <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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The added weak symbol must not be static.
This was introduced in 416ce623fbad51af57660346ebb6f7befb88b3c9
Signed-off-by: Joe Hershberger <[email protected]>
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SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently there is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashim <[email protected]>
Signed-off-by: Vipin Kumar <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Do not select MIIPORT for RGMII interface
Signed-off-by: Vipin Kumar <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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This add phylib support to the Marvell GBE driver.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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This adds PHY initialization for Marvell Alaska 88E1310 PHY.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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The driver code was taken from Linux kernel source:
drivers/net/phy/icplus.c
Signed-off-by: Yegor Yefremov <[email protected]>
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Signed-off-by: Yegor Yefremov <[email protected]>
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This patch adds support for the WEMAC, the ethernet controller included
in the Allwinner A10 SoC. It will get used in the upcoming A10 board
support.
From: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Henrik Nordstrom <[email protected]>
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before writing the received buffer to nand, erase the nand
sectors. If not doing this, nand write fails. See for
more info here:
http://lists.denx.de/pipermail/u-boot/2013-June/156361.html
Using the nand erase option "spread", maybe overwrite
blocks on, for example another mtd partition, if the
erasing range contains bad blocks.
So a limit option is added to nand_erase_opts()
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Lukasz Majewski <[email protected]>
Cc: Kyungmin Park <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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This patch adds FDT support to the serial s5p driver.
At present disabling the serial console (from the device tree) crashes
U-Boot. Add checks for this case, so that execution can continue without
a serial console.
It also enables the serial_s5p driver recognize the silent_console option.
Signed-off-by: Abhilash Kesavan <[email protected]>
Signed-off-by: Gabe Black <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch updates the function board_i2c_init() to add support for both
FDT and non-FDT for I2C, and initialise the I2C channels.
Signed-off-by: Amar <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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- Added debug's on spi_flash_read_common()
- Added space
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Placed the sf calls in proper order - erase/write/read
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Move common flash write code into spi_flash_write_common().
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for Spansion S25FL512S_64K SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q1024A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q1024 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q512A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Add support for Numonyx N25Q512 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)
With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.
As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki <[email protected]>
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